or2a.vhd

利用两个半加器来组成的全加器

library ieee;
use ieee.std_logic_1164.all;
entity or2a is 
  port(a,b:in std_logic;
         c:out std_logic);
end entity or2a;
architecture one of or2a is 
  begin 
   c<=a or b;
end architecture one;