h_adder.vhd

来自「利用两个半加器来组成的全加器」· VHDL 代码 · 共 10 行

library ieee;
use ieee.std_logic_1164.all;
entity h_adder is 
  port (a,b:in std_logic;
        co,so:out std_logic);
end entity h_adder;
architecture fh1 of h_adder is
begin
  so<=not(a xor(not b));  co<=a and b;
end architecture fh1;