f_adder.vhd

来自「利用两个半加器来组成的全加器」· VHDL 代码 · 共 21 行

library ieee;
use ieee.std_logic_1164.all;
entity f_adder is
  port(ain,bin,cin:in std_logic;
         cout,sum:out std_logic);
end entity f_adder;
architecture fd1 of f_adder is
  component h_adder
    port(a,b:in std_logic;
         co,so:out std_logic);
  end component;
  component or2a
    port(a,b:in std_logic;
          c:out std_logic);
  end component;
 signal d,e,f:std_logic;
  begin
    u1:h_adder port map(a=>ain,b=>bin,co=>d,so=>e);
    u2:h_adder port map(a=>e,b=>cin,co=>f,so=>sum);
    u3:  or2a  port map(a=>d,b=>f,c=>cout);
end architecture fd1;