_primary.vhd

用4位十进制计数器对用户输入时钟信号进行计数

library verilog;
use verilog.vl_types.all;
entity reg4b is
    port(
        loadi           : in     vl_logic;
        din             : in     vl_logic_vector(3 downto 0);
        dout            : out    vl_logic_vector(3 downto 0)
    );
end reg4b;