_primary.vhd

来自「用4位十进制计数器对用户输入时钟信号进行计数」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity cnt10 is
    port(
        clkk            : in     vl_logic;
        rst             : in     vl_logic;
        ena             : in     vl_logic;
        outy            : out    vl_logic_vector(3 downto 0);
        cout            : out    vl_logic
    );
end cnt10;