📄 half_ad.tan.rpt
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Classic Timing Analyzer report for half_ad
Mon Mar 23 16:17:20 2009
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 12.453 ns ; a[0] ; s[3] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C12Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 12.453 ns ; a[0] ; s[3] ;
; N/A ; None ; 12.429 ns ; b[0] ; s[3] ;
; N/A ; None ; 12.191 ns ; a[1] ; s[3] ;
; N/A ; None ; 12.187 ns ; b[1] ; s[3] ;
; N/A ; None ; 12.035 ns ; a[0] ; s[4] ;
; N/A ; None ; 12.011 ns ; b[0] ; s[4] ;
; N/A ; None ; 11.879 ns ; a[0] ; s[2] ;
; N/A ; None ; 11.855 ns ; b[0] ; s[2] ;
; N/A ; None ; 11.773 ns ; a[1] ; s[4] ;
; N/A ; None ; 11.769 ns ; b[1] ; s[4] ;
; N/A ; None ; 11.618 ns ; b[2] ; s[3] ;
; N/A ; None ; 11.617 ns ; a[1] ; s[2] ;
; N/A ; None ; 11.613 ns ; b[1] ; s[2] ;
; N/A ; None ; 11.465 ns ; a[2] ; s[3] ;
; N/A ; None ; 11.200 ns ; b[2] ; s[4] ;
; N/A ; None ; 11.052 ns ; a[3] ; s[3] ;
; N/A ; None ; 11.047 ns ; a[2] ; s[4] ;
; N/A ; None ; 11.041 ns ; b[2] ; s[2] ;
; N/A ; None ; 10.890 ns ; a[2] ; s[2] ;
; N/A ; None ; 10.824 ns ; b[3] ; s[3] ;
; N/A ; None ; 10.708 ns ; b[0] ; s[0] ;
; N/A ; None ; 10.633 ns ; a[3] ; s[4] ;
; N/A ; None ; 10.542 ns ; a[0] ; s[1] ;
; N/A ; None ; 10.520 ns ; b[0] ; s[1] ;
; N/A ; None ; 10.405 ns ; b[3] ; s[4] ;
; N/A ; None ; 10.282 ns ; a[1] ; s[1] ;
; N/A ; None ; 10.278 ns ; b[1] ; s[1] ;
; N/A ; None ; 10.247 ns ; a[0] ; s[0] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
Info: Processing started: Mon Mar 23 16:17:19 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off half_ad -c half_ad --timing_analysis_only
Info: Longest tpd from source pin "a[0]" to destination pin "s[3]" is 12.453 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_235; Fanout = 3; PIN Node = 'a[0]'
Info: 2: + IC(5.133 ns) + CELL(0.590 ns) = 7.198 ns; Loc. = LC_X4_Y26_N9; Fanout = 2; COMB Node = 'adder:inst1|inst2~3'
Info: 3: + IC(0.449 ns) + CELL(0.292 ns) = 7.939 ns; Loc. = LC_X4_Y26_N6; Fanout = 2; COMB Node = 'adder:inst2|inst2~70'
Info: 4: + IC(0.448 ns) + CELL(0.114 ns) = 8.501 ns; Loc. = LC_X4_Y26_N5; Fanout = 1; COMB Node = 'adder:inst3|half_ad:inst1|inst1'
Info: 5: + IC(1.828 ns) + CELL(2.124 ns) = 12.453 ns; Loc. = PIN_3; Fanout = 0; PIN Node = 's[3]'
Info: Total cell delay = 4.595 ns ( 36.90 % )
Info: Total interconnect delay = 7.858 ns ( 63.10 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Allocated 100 megabytes of memory during processing
Info: Processing ended: Mon Mar 23 16:17:20 2009
Info: Elapsed time: 00:00:01
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