📄 mips2000.bde
字号:
}
NET WIRE 3154, 0, 0
{
VARIABLES
{
#NAME="mw"
}
}
TEXT 3155, 0, 0
{
TEXT "$#NAME"
RECT (641,471,680,500)
ALIGN 9
MARGINS (1,1)
PARENT 4991
}
TEXT 3159, 0, 0
{
TEXT "$#NAME"
RECT (1304,811,1336,840)
ALIGN 9
MARGINS (1,1)
PARENT 5003
}
NET BUS 3163, 0, 0
{
VARIABLES
{
#NAME="op(5:0)"
#VERILOG_TYPE="wire"
}
}
TEXT 3164, 0, 0
{
TEXT "$#NAME"
RECT (1260,1106,1338,1135)
ALIGN 4
MARGINS (1,1)
PARENT 5000
}
TEXT 3168, 0, 0
{
TEXT "$#NAME"
RECT (1901,711,1979,740)
ALIGN 9
MARGINS (1,1)
PARENT 5057
}
NET WIRE 3172, 0, 0
{
VARIABLES
{
#NAME="zero"
}
}
TEXT 3173, 0, 0
{
TEXT "$#NAME"
RECT (1476,891,1524,920)
ALIGN 9
MARGINS (1,1)
PARENT 5075
}
NET WIRE 3177, 0, 0
{
VARIABLES
{
#NAME="neg"
}
}
TEXT 3178, 0, 0
{
TEXT "$#NAME"
RECT (1499,971,1542,1000)
ALIGN 9
MARGINS (1,1)
PARENT 5070
}
NET WIRE 3185, 0, 0
{
VARIABLES
{
#NAME="reset"
}
}
NET WIRE 3190, 0, 0
{
VARIABLES
{
#NAME="MBRld"
}
}
TEXT 3191, 0, 0
{
TEXT "$#NAME"
RECT (593,270,667,299)
ALIGN 9
MARGINS (1,1)
PARENT 4986
}
NET WIRE 3195, 0, 0
{
VARIABLES
{
#NAME="IRld"
}
}
TEXT 3196, 0, 0
{
TEXT "$#NAME"
RECT (1028,270,1073,299)
ALIGN 9
MARGINS (1,1)
PARENT 4988
}
NET WIRE 3331, 0, 0
{
VARIABLES
{
#NAME="PCld"
}
}
TEXT 3332, 0, 0
{
TEXT "$#NAME"
RECT (213,891,268,920)
ALIGN 9
MARGINS (1,1)
PARENT 5035
}
NET WIRE 3336, 0, 0
{
VARIABLES
{
#NAME="PCsel"
}
}
TEXT 3337, 0, 0
{
TEXT "$#NAME"
RECT (207,931,273,960)
ALIGN 9
MARGINS (1,1)
PARENT 5034
}
NET WIRE 3341, 0, 0
{
VARIABLES
{
#NAME="regWrite"
}
}
TEXT 3342, 0, 0
{
TEXT "$#NAME"
RECT (660,786,753,815)
ALIGN 4
MARGINS (1,1)
PARENT 5032
}
NET WIRE 3346, 0, 0
{
VARIABLES
{
#NAME="wrDataSel"
}
}
TEXT 3347, 0, 0
{
TEXT "$#NAME"
RECT (760,766,872,795)
ALIGN 4
MARGINS (1,1)
PARENT 5031
}
NET WIRE 3351, 0, 0
{
VARIABLES
{
#NAME="wrRegSel"
}
}
TEXT 3352, 0, 0
{
TEXT "$#NAME"
RECT (880,786,986,815)
ALIGN 4
MARGINS (1,1)
PARENT 5030
}
NET WIRE 3356, 0, 0
{
VARIABLES
{
#NAME="srcA"
}
}
TEXT 3357, 0, 0
{
TEXT "$#NAME"
RECT (1180,786,1229,815)
ALIGN 4
MARGINS (1,1)
PARENT 4999
}
NET BUS 3365, 0, 0
{
VARIABLES
{
#NAME="srcB(1:0)"
#VERILOG_TYPE="wire"
}
}
TEXT 3366, 0, 0
{
TEXT "$#NAME"
RECT (1080,1106,1179,1135)
ALIGN 4
MARGINS (1,1)
PARENT 5036
}
NET WIRE 3370, 0, 0
{
VARIABLES
{
#NAME="RegBmdEN"
}
}
TEXT 3371, 0, 0
{
TEXT "$#NAME"
RECT (856,611,985,640)
ALIGN 9
MARGINS (1,1)
PARENT 4984
}
NET WIRE 3375, 0, 0
{
VARIABLES
{
#NAME="ALUmaEN"
}
}
TEXT 3376, 0, 0
{
TEXT "$#NAME"
RECT (1264,611,1377,640)
ALIGN 9
MARGINS (1,1)
PARENT 4983
}
NET WIRE 3380, 0, 0
{
VARIABLES
{
#NAME="PCmaEN"
}
}
TEXT 3381, 0, 0
{
TEXT "$#NAME"
RECT (550,611,651,640)
ALIGN 9
MARGINS (1,1)
PARENT 4985
}
TEXT 3385, 0, 0
{
TEXT "$#NAME"
RECT (1904,351,2017,380)
ALIGN 9
MARGINS (1,1)
PARENT 5056
}
TEXT 3389, 0, 0
{
TEXT "$#NAME"
RECT (1898,391,1943,420)
ALIGN 9
MARGINS (1,1)
PARENT 5055
}
TEXT 3393, 0, 0
{
TEXT "$#NAME"
RECT (1903,431,1977,460)
ALIGN 9
MARGINS (1,1)
PARENT 5054
}
TEXT 3397, 0, 0
{
TEXT "$#NAME"
RECT (1893,471,1948,500)
ALIGN 9
MARGINS (1,1)
PARENT 5053
}
TEXT 3401, 0, 0
{
TEXT "$#NAME"
RECT (1890,511,1991,540)
ALIGN 9
MARGINS (1,1)
PARENT 5052
}
TEXT 3405, 0, 0
{
TEXT "$#NAME"
RECT (1887,551,1953,580)
ALIGN 9
MARGINS (1,1)
PARENT 5051
}
TEXT 3409, 0, 0
{
TEXT "$#NAME"
RECT (1896,591,2025,620)
ALIGN 9
MARGINS (1,1)
PARENT 5050
}
TEXT 3413, 0, 0
{
TEXT "$#NAME"
RECT (1905,631,1935,660)
ALIGN 9
MARGINS (1,1)
PARENT 5049
}
TEXT 3417, 0, 0
{
TEXT "$#NAME"
RECT (1901,671,1940,700)
ALIGN 9
MARGINS (1,1)
PARENT 5048
}
TEXT 3421, 0, 0
{
TEXT "$#NAME"
RECT (1894,751,1987,780)
ALIGN 9
MARGINS (1,1)
PARENT 5047
}
TEXT 3425, 0, 0
{
TEXT "$#NAME"
RECT (1896,791,1945,820)
ALIGN 9
MARGINS (1,1)
PARENT 5046
}
TEXT 3429, 0, 0
{
TEXT "$#NAME"
RECT (1891,831,1990,860)
ALIGN 9
MARGINS (1,1)
PARENT 5058
}
TEXT 3433, 0, 0
{
TEXT "$#NAME"
RECT (1884,871,1996,900)
ALIGN 9
MARGINS (1,1)
PARENT 5045
}
TEXT 3437, 0, 0
{
TEXT "$#NAME"
RECT (1887,911,1993,940)
ALIGN 9
MARGINS (1,1)
PARENT 5044
}
INSTANCE 3441, 0, 0
{
VARIABLES
{
#COMPONENT="Power"
#LIBRARY="#connectors"
#REFERENCE="VCC"
#SYMBOL="Power"
}
COORD (1300,740)
ORIENTATION 2
VERTEXES ( (2,4907) )
}
TEXT 3442, 0, 0
{
TEXT "$#REFERENCE"
RECT (1226,693,1289,728)
ALIGN 6
MARGINS (1,1)
PARENT 3441
}
INSTANCE 3479, 0, 0
{
VARIABLES
{
#COMPONENT="Input"
#LIBRARY="#terminals"
#REFERENCE="clk"
#SYMBOL="Input"
}
COORD (260,1160)
VERTEXES ( (2,5079) )
}
TEXT 3480, 0, 0
{
TEXT "$#REFERENCE"
RECT (202,1163,240,1198)
ALIGN 6
MARGINS (1,1)
PARENT 3479
}
TEXT 3493, 0, 0
{
TEXT "$#NAME"
RECT (1593,731,1648,760)
ALIGN 9
MARGINS (1,1)
PARENT 5043
}
INSTANCE 3497, 0, 0
{
VARIABLES
{
#COMPONENT="Input"
#LIBRARY="#terminals"
#REFERENCE="reset"
#SYMBOL="Input"
}
COORD (260,1000)
VERTEXES ( (2,5082) )
}
TEXT 3498, 0, 0
{
TEXT "$#REFERENCE"
RECT (193,1003,260,1038)
ALIGN 6
MARGINS (1,1)
PARENT 3497
}
TEXT 3531, 0, 0
{
TEXT "$#NAME"
RECT (1040,406,1303,435)
ALIGN 4
MARGINS (1,1)
PARENT 4949
}
NET BUS 3535, 0, 0
{
VARIABLES
{
#NAME="memory_data_bus(31:0)"
#VERILOG_TYPE="wire"
}
}
NET BUS 3536, 0, 0
{
VARIABLES
{
#NAME="memory_address_bus(31:0)"
#VERILOG_TYPE="wire"
}
}
TEXT 3537, 0, 0
{
TEXT "$#NAME"
RECT (1129,531,1431,560)
ALIGN 9
MARGINS (1,1)
PARENT 4957
}
VTX 4829, 0, 0
{
COORD (940,400)
}
VTX 4830, 0, 0
{
COORD (940,380)
}
VTX 4831, 0, 0
{
COORD (840,400)
}
VTX 4832, 0, 0
{
COORD (840,420)
}
VTX 4833, 0, 0
{
COORD (740,380)
}
VTX 4834, 0, 0
{
COORD (840,540)
}
VTX 4835, 0, 0
{
COORD (840,560)
}
VTX 4836, 0, 0
{
COORD (1420,580)
}
VTX 4837, 0, 0
{
COORD (640,1200)
}
VTX 4838, 0, 0
{
COORD (1420,960)
}
VTX 4839, 0, 0
{
COORD (1020,580)
}
VTX 4840, 0, 0
{
COORD (1020,1020)
}
VTX 4841, 0, 0
{
COORD (1020,700)
}
VTX 4842, 0, 0
{
COORD (700,740)
}
VTX 4843, 0, 0
{
COORD (700,700)
}
VTX 4844, 0, 0
{
COORD (700,580)
}
VTX 4845, 0, 0
{
COORD (600,1240)
}
VTX 4846, 0, 0
{
COORD (280,880)
}
VTX 4847, 0, 0
{
COORD (320,1040)
}
VTX 4848, 0, 0
{
COORD (320,880)
}
VTX 4849, 0, 0
{
COORD (940,260)
}
VTX 4850, 0, 0
{
COORD (940,200)
}
VTX 4851, 0, 0
{
COORD (1360,640)
}
VTX 4852, 0, 0
{
COORD (1340,640)
}
VTX 4853, 0, 0
{
COORD (960,640)
}
VTX 4854, 0, 0
{
COORD (940,640)
}
VTX 4855, 0, 0
{
COORD (640,640)
}
VTX 4856, 0, 0
{
COORD (620,640)
}
VTX 4857, 0, 0
{
COORD (640,300)
}
VTX 4858, 0, 0
{
COORD (620,300)
}
VTX 4859, 0, 0
{
COORD (640,340)
}
VTX 4860, 0, 0
{
COORD (620,340)
}
VTX 4861, 0, 0
{
COORD (1040,300)
}
VTX 4862, 0, 0
{
COORD (1060,300)
}
VTX 4863, 0, 0
{
COORD (1040,340)
}
VTX 4864, 0, 0
{
COORD (1060,340)
}
VTX 4865, 0, 0
{
COORD (680,460)
}
VTX 4866, 0, 0
{
COORD (660,460)
}
VTX 4867, 0, 0
{
COORD (680,500)
}
VTX 4868, 0, 0
{
COORD (660,500)
}
VTX 4869, 0, 0
{
COORD (1080,1040)
}
VTX 4870, 0, 0
{
COORD (1360,960)
}
VTX 4871, 0, 0
{
COORD (1080,1020)
}
VTX 4872, 0, 0
{
COORD (1180,820)
}
VTX 4873, 0, 0
{
COORD (1180,800)
}
VTX 4874, 0, 0
{
COORD (1260,1120)
}
VTX 4875, 0, 0
{
COORD (1260,1140)
}
VTX 4876, 0, 0
{
COORD (1420,840)
}
VTX 4877, 0, 0
{
COORD (1420,700)
}
VTX 4878, 0, 0
{
COORD (1420,720)
}
VTX 4879, 0, 0
{
COORD (1300,800)
}
VTX 4880, 0, 0
{
COORD (1320,800)
}
VTX 4883, 0, 0
{
COORD (1080,900)
}
VTX 4884, 0, 0
{
COORD (580,880)
}
VTX 4885, 0, 0
{
COORD (680,1040)
}
VTX 4886, 0, 0
{
COORD (1080,920)
}
VTX 4887, 0, 0
{
COORD (960,920)
}
VTX 4888, 0, 0
{
COORD (680,980)
}
VTX 4889, 0, 0
{
COORD (960,1020)
}
VTX 4890, 0, 0
{
COORD (740,260)
}
VTX 4891, 0, 0
{
COORD (680,920)
}
VTX 4892, 0, 0
{
COORD (880,820)
}
VTX 4893, 0, 0
{
COORD (880,800)
}
VTX 4894, 0, 0
{
COORD (820,820)
}
VTX 4895, 0, 0
{
COORD (820,800)
}
VTX 4896, 0, 0
{
COORD (760,820)
}
VTX 4897, 0, 0
{
COORD (760,800)
}
VTX 4898, 0, 0
{
COORD (820,1120)
}
VTX 4899, 0, 0
{
COORD (820,1160)
}
VTX 4900, 0, 0
{
COORD (320,960)
}
VTX 4901, 0, 0
{
COORD (240,960)
}
VTX 4902, 0, 0
{
COORD (320,920)
}
VTX 4903, 0, 0
{
COORD (240,920)
}
VTX 4904, 0, 0
{
COORD (1180,1120)
}
VTX 4905, 0, 0
{
COORD (1180,1140)
}
VTX 4906, 0, 0
{
COORD (1320,760)
}
VTX 4907, 0, 0
{
COORD (1300,740)
}
VTX 4908, 0, 0
{
COORD (440,1120)
}
VTX 4909, 0, 0
{
COORD (440,1160)
}
VTX 4911, 0, 0
{
COORD (1640,760)
}
VTX 4912, 0, 0
{
COORD (1620,760)
}
VTX 4913, 0, 0
{
COORD (1880,940)
}
VTX 4914, 0, 0
{
COORD (1900,940)
}
VTX 4915, 0, 0
{
COORD (1880,900)
}
VTX 4916, 0, 0
{
COORD (1900,900)
}
VTX 4917, 0, 0
{
COORD (1880,820)
}
VTX 4918, 0, 0
{
COORD (1900,820)
}
VTX 4919, 0, 0
{
COORD (1880,780)
}
VTX 4920, 0, 0
{
COORD (1900,780)
}
VTX 4921, 0, 0
{
COORD (1880,700)
}
VTX 4922, 0, 0
{
COORD (1900,700)
}
VTX 4923, 0, 0
{
COORD (1880,660)
}
VTX 4924, 0, 0
{
COORD (1900,660)
}
VTX 4925, 0, 0
{
COORD (1880,620)
}
VTX 4926, 0, 0
{
COORD (1900,620)
}
VTX 4927, 0, 0
{
COORD (1880,580)
}
VTX 4928, 0, 0
{
COORD (1900,580)
}
VTX 4929, 0, 0
{
COORD (1880,540)
}
VTX 4930, 0, 0
{
COORD (1900,540)
}
VTX 4931, 0, 0
{
COORD (1880,500)
}
VTX 4932, 0, 0
{
COORD (1900,500)
}
VTX 4933, 0, 0
{
COORD (1880,460)
}
VTX 4934, 0, 0
{
COORD (1900,460)
}
VTX 4935, 0, 0
{
COORD (1880,420)
}
VTX 4936, 0, 0
{
COORD (1900,420)
}
VTX 4937, 0, 0
{
COORD (1880,380)
}
VTX 4938, 0, 0
{
COORD (1900,380)
}
VTX 4939, 0, 0
{
COORD (1880,740)
}
VTX 4940, 0, 0
{
COORD (1900,740)
}
VTX 4941, 0, 0
{
COORD (1880,860)
}
VTX 4942, 0, 0
{
COORD (1900,860)
}
VTX 4943, 0, 0
{
COORD (1640,940)
}
VTX 4944, 0, 0
{
COORD (1640,380)
}
VTX 4945, 0, 0
{
COORD (1360,1000)
}
VTX 4946, 0, 0
{
COORD (1640,580)
}
VTX 4947, 0, 0
{
COORD (1360,920)
}
VTX 4948, 0, 0
{
COORD (1640,540)
}
BUS 4949, 0, 0
{
NET 3535
VTX 4829, 4830
VARIABLES
{
#NAMED="1"
}
}
BUS 4950, 0, 0
{
NET 3535
VTX 4829, 4831
}
BUS 4951, 0, 0
{
NET 3535
VTX 4832, 4831
}
VTX 4952, 0, 0
{
COORD (740,400)
}
BUS 4953, 0, 0
{
NET 3535
VTX 4831, 4952
}
BUS 4954, 0, 0
{
NET 3535
VTX 4952, 4833
}
BUS 4955, 0, 0
{
NET 3536
VTX 4834, 4835
}
VTX 4956, 0, 0
{
COORD (1420,560)
}
BUS 4957, 0, 0
{
NET 3536
VTX 4835, 4956
VARIABLES
{
#NAMED="1"
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -