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}
PIN 8, 0, 0
{
COORD (0,80)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#NAME="write"
#NUMBER="0"
#SIDE="left"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
}
}
}
SYMBOL "#default" "PC" "PC"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1109673056"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,260,280)
FREEID 26
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,0,240,260)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,190,140,214)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (156,30,235,54)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (25,30,108,54)
ALIGN 4
MARGINS (1,1)
PARENT 6
}
TEXT 9, 0, 0
{
TEXT "$#NAME"
RECT (25,70,69,94)
ALIGN 4
MARGINS (1,1)
PARENT 8
}
TEXT 11, 0, 0
{
TEXT "$#NAME"
RECT (25,110,79,134)
ALIGN 4
MARGINS (1,1)
PARENT 10
}
TEXT 15, 0, 0
{
TEXT "$#NAME"
RECT (25,150,70,174)
ALIGN 4
MARGINS (1,1)
PARENT 14
}
TEXT 25, 0, 0
{
TEXT "$#NAME"
RECT (115,228,140,252)
ALIGN 6
MARGINS (1,1)
PARENT 24
}
PIN 2, 0, 0
{
COORD (0,200)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#NAME="ALUout(31:0)"
#NUMBER="0"
#SIDE="left"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (260,40)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#NAME="PC(31:0)"
#NUMBER="0"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#NAME="Inst(31:0)"
#NUMBER="0"
#SIDE="left"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 8, 0, 0
{
COORD (0,80)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#NAME="PCld"
#NUMBER="0"
#SIDE="left"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 10, 0, 0
{
COORD (0,120)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#NAME="PCsel"
#NUMBER="0"
#SIDE="left"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 14, 0, 0
{
COORD (0,160)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#NAME="reset"
#NUMBER="0"
#SIDE="left"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 24, 0, 0
{
COORD (120,280)
VARIABLES
{
#DIRECTION="IN"
#LABEL="CLK"
#LENGTH="20"
#MODIFIED=""
#NAME="clk"
#NUMBER="1"
#SIDE="bottom"
}
LINE 1, 0, 0
{
OUTLINE 0,1, (0,0,128)
POINTS ( (0,0), (0,-20) )
}
LINE 2, 0, 0
{
OUTLINE 0,1, (0,0,128)
POINTS ( (0,-20), (-10,-20), (0,-30), (10,-20), (0,-20) )
}
}
}
}
}
SYMBOL "#default" "Reg32_LD" "Reg32_LD"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1109673102"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,180,120)
FREEID 16
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,20,180,100)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (74,68,140,92)
ALIGN 6
MARGINS (1,1)
PARENT 2
ORIENTATION 4
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (80,28,147,52)
ALIGN 4
MARGINS (1,1)
PARENT 4
ORIENTATION 2
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (25,30,52,54)
ALIGN 4
MARGINS (1,1)
PARENT 6
}
TEXT 15, 0, 0
{
TEXT "$#NAME"
RECT (34,68,59,92)
ALIGN 4
MARGINS (1,1)
PARENT 14
}
PIN 2, 0, 0
{
COORD (100,120)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#NAME="D(31:0)"
#NUMBER="0"
#SIDE="bottom"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (0,-20) )
}
}
PIN 4, 0, 0
{
COORD (100,0)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#NAME="Q(31:0)"
#NUMBER="0"
#SIDE="top"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (0,20), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (0,40)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#NAME="LD"
#NUMBER="0"
#SIDE="left"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 14, 0, 0
{
COORD (0,80)
VARIABLES
{
#DIRECTION="IN"
#LABEL="CLK"
#LENGTH="20"
#MODIFIED=""
#NAME="clk"
#NUMBER="1"
#SIDE="left"
}
LINE 1, 0, 0
{
OUTLINE 0,1, (0,0,128)
POINTS ( (0,0), (20,0) )
}
LINE 2, 0, 0
{
OUTLINE 0,1, (0,0,128)
POINTS ( (20,0), (20,-10), (30,0), (20,10), (20,0) )
}
}
}
}
}
SYMBOL "#default" "RegFile" "RegFile"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1109672999"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,280,300)
FREEID 37
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,20,260,280)
}
TEXT 3, 0, 0
{
TEXT "$#NAME"
RECT (25,210,140,234)
ALIGN 4
MARGINS (1,1)
PARENT 2
}
TEXT 5, 0, 0
{
TEXT "$#NAME"
RECT (159,88,260,112)
ALIGN 6
MARGINS (1,1)
PARENT 4
}
TEXT 7, 0, 0
{
TEXT "$#NAME"
RECT (25,150,108,174)
ALIGN 4
MARGINS (1,1)
PARENT 6
}
TEXT 9, 0, 0
{
TEXT "$#NAME"
RECT (159,188,260,212)
ALIGN 6
MARGINS (1,1)
PARENT 8
}
TEXT 11, 0, 0
{
TEXT "$#NAME"
RECT (25,90,119,114)
ALIGN 4
MARGINS (1,1)
PARENT 10
}
TEXT 15, 0, 0
{
TEXT "$#NAME"
RECT (40,28,115,52)
ALIGN 4
MARGINS (1,1)
PARENT 14
}
TEXT 17, 0, 0
{
TEXT "$#NAME"
RECT (100,48,188,72)
ALIGN 4
MARGINS (1,1)
PARENT 16
}
TEXT 19, 0, 0
{
TEXT "$#NAME"
RECT (160,28,245,52)
ALIGN 4
MARGINS (1,1)
PARENT 18
}
TEXT 36, 0, 0
{
TEXT "$#NAME"
RECT (135,248,160,272)
ALIGN 6
MARGINS (1,1)
PARENT 35
}
PIN 2, 0, 0
{
COORD (0,220)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#NAME="ALUout(31:0)"
#NUMBER="0"
#SIDE="left"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (280,100)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#NAME="RegA(31:0)"
#NUMBER="0"
#SIDE="right"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (0,160)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#NAME="Inst(31:0)"
#NUMBER="0"
#SIDE="left"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 8, 0, 0
{
COORD (280,200)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#NAME="RegB(31:0)"
#NUMBER="0"
#SIDE="right"
#VERILOG_TYPE="reg"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 10, 0, 0
{
COORD (0,100)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#NAME="MBR(31:0)"
#NUMBER="0"
#SIDE="left"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 14, 0, 0
{
COORD (80,0)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#NAME="regWrite"
#NUMBER="0"
#SIDE="top"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (0,20) )
}
}
PIN 16, 0, 0
{
COORD (140,0)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#NAME="wrDataSel"
#NUMBER="0"
#SIDE="top"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (0,20) )
}
}
PIN 18, 0, 0
{
COORD (200,0)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#NAME="wrRegSel"
#NUMBER="0"
#SIDE="top"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (0,20) )
}
}
PIN 35, 0, 0
{
COORD (140,300)
VARIABLES
{
#DIRECTION="IN"
#LABEL="CLK"
#LENGTH="20"
#MODIFIED=""
#NAME="clk"
#NUMBER="1"
#SIDE="bottom"
}
LINE 1, 0, 0
{
OUTLINE 0,1, (0,0,128)
POINTS ( (0,0), (0,-20) )
}
LINE 2, 0, 0
{
OUTLINE 0,1, (0,0,128)
POINTS ( (0,-20), (-10,-20), (0,-30), (10,-20), (0,-20) )
}
}
}
}
}
SYMBOL "#default" "Tri32" "Tri32"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1109630062"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (40,0,160,120)
FREEID 27
}
BODY
{
LINE 25, 0, 0
{
OUTLINE 0,1, (0,0,0)
POINTS ( (100,20), (100,40) )
FILL (1,(0,0,0),0)
}
GROUP 26, -1, 0
{
RECT (60,20,140,100)
VARIABLES
{
#NAME="BUF"
#OUTLINE_FILLING="1"
}
FREEID 1
LINE 13, 0, 0
{
OUTLINE 0,2, (132,4,0)
POINTS ( (0,0), (79,39), (0,79), (0,0) )
FILL (0,(255,255,156),0)
}
}
PIN 2, 0, 0
{
COORD (40,60)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#NAME="I(31:0)"
#NUMBER="0"
#SIDE="left"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 4, 0, 0
{
COORD (160,60)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#NAME="O(31:0)"
#NUMBER="0"
#SIDE="right"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 6, 0, 0
{
COORD (100,0)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#NAME="OE"
#NUMBER="0"
#SIDE="top"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (0,20) )
}
}
}
}
}
}
PAGE ""
{
PAGEHEADER
{
PAGESIZE (2200,1700)
MARGINS (200,200,200,200)
RECT (0,0,100,200)
}
BODY
{
INSTANCE 109, 0, 0
{
VARIABLES
{
#COMPONENT="ALU"
#LIBRARY="#default"
#REFERENCE="U4"
#SYMBOL="ALU"
}
COORD (1100,800)
VERTEXES ( (6,4883), (10,4886), (14,4871), (2,4869), (18,4872), (20,4904), (16,4874), (12,4947), (4,4870), (8,4945) )
PINPROP 12,"#PIN_STATE","0"
}
TEXT 114, 0, 0
{
TEXT "$#COMPONENT"
RECT (1100,960,1158,995)
MARGINS (1,1)
PARENT 109
}
INSTANCE 118, 0, 0
{
VARIABLES
{
#COMPONENT="PC"
#LIBRARY="#default"
#REFERENCE="U5"
#SYMBOL="PC"
}
COORD (320,840)
VERTEXES ( (6,4848), (8,4902), (10,4900), (2,4847), (24,4908), (4,4884), (14,5081) )
PINPROP 14,"#PIN_STATE","0"
}
TEXT 123, 0, 0
{
TEXT "$#COMPONENT"
RECT (340,1100,382,1135)
MARGINS (1,1)
PARENT 118
}
INSTANCE 127, 0, 0
{
VARIABLES
{
#COMPONENT="RegFile"
#LIBRARY="#default"
#REFERENCE="U6"
#SYMBOL="RegFile"
}
COORD (680,820)
VERTEXES ( (10,4891), (6,4888), (2,4885), (14,4896), (16,4894), (35,4898), (18,4892), (4,4887), (8,4889) )
PINPROP 35,"#PIN_STATE","0"
}
TEXT 132, 0, 0
{
TEXT "$#COMPONENT"
RECT (700,1101,803,1136)
MARGINS (1,1)
PARENT 127
}
INSTANCE 207, 0, 0
{
VARIABLES
{
#COMPONENT="Controller"
#LIBRARY="#default"
#REFERENCE="U11"
#SYMBOL="Controller"
}
COORD (1640,340)
VERTEXES ( (2,4944), (18,4948), (10,4946), (14,4911), (44,4943), (4,4937), (8,4935), (12,4933), (16,4931), (20,4929), (22,4927), (24,4925), (26,4923), (28,4921), (30,4939), (32,4919), (34,4917), (36,4941), (38,4915), (40,4913) )
PINPROP 2,"#PIN_STATE","0"
}
TEXT 212, 0, 0
{
TEXT "$#COMPONENT"
RECT (1660,980,1789,1015)
MARGINS (1,1)
PARENT 207
}
NET BUS 255, 0, 0
NET BUS 692, 0, 0
NET BUS 699, 0, 0
INSTANCE 1233, 0, 0
{
VARIABLES
{
#COMPONENT="Tri32"
#LIBRARY="#default"
#REFERENCE="U14"
#SYMBOL="Tri32"
}
COORD (640,740)
ORIENTATION 8
VERTEXES ( (6,4855), (4,4844), (2,4843) )
PINPROP 6,"#PIN_STATE","0"
}
INSTANCE 1384, 0, 0
{
VARIABLES
{
#COMPONENT="Memory"
#LIBRARY="#default"
#REFERENCE="U9"
#SYMBOL="Memory"
}
COORD (680,420)
VERTEXES ( (6,4865), (8,4867), (4,4832), (2,4834) )
PINPROP 8,"#PIN_STATE","0"
}
TEXT 1389, 0, 0
{
TEXT "$#COMPONENT"
RECT (700,520,805,555)
MARGINS (1,1)
PARENT 1384
}
INSTANCE 1425, 0, 0
{
VARIABLES
{
#COMPONENT="Reg32_LD"
#LIBRARY="#default"
#REFERENCE="U15"
#SYMBOL="Reg32_LD"
}
COORD (1040,260)
ORIENTATION 2
VERTEXES ( (4,4849), (2,4830), (6,4861), (14,4863) )
PINPROP 14,"#PIN_STATE","0"
}
NET BUS 1633, 0, 0
INSTANCE 1689, 0, 0
{
VARIABLES
{
#COMPONENT="Reg32_LD"
#LIBRARY="#default"
#REFERENCE="U1"
#SYMBOL="Reg32_LD"
}
COORD (640,260)
VERTEXES ( (6,4857), (14,4859), (4,4890), (2,4833) )
PINPROP 4,"#PIN_STATE","0"
}
INSTANCE 1745, 0, 0
{
VARIABLES
{
#COMPONENT="Tri32"
#LIBRARY="#default"
#REFERENCE="U2"
#SYMBOL="Tri32"
}
COORD (960,740)
ORIENTATION 8
VERTEXES ( (6,4853), (4,4839), (2,4841) )
PINPROP 6,"#PIN_STATE","0"
}
INSTANCE 1746, 0, 0
{
VARIABLES
{
#COMPONENT="Tri32"
#LIBRARY="#default"
#REFERENCE="U7"
#SYMBOL="Tri32"
}
COORD (1360,740)
ORIENTATION 8
VERTEXES ( (6,4851), (4,4836), (2,4877) )
PINPROP 2,"#PIN_STATE","0"
}
INSTANCE 1767, 0, 0
{
VARIABLES
{
#COMPONENT="Reg32_LD"
#LIBRARY="#default"
#REFERENCE="U3"
#SYMBOL="Reg32_LD"
}
COORD (1320,720)
VERTEXES ( (6,4906), (14,4880), (4,4878), (2,4876) )
PINPROP 6,"#PIN_STATE","0"
}
NET BUS 1803, 0, 0
NET BUS 2451, 0, 0
NET WIRE 2499, 0, 0
NET BUS 2807, 0, 0
NET WIRE 3052, 0, 0
{
VARIABLES
{
#NAME="clk"
}
}
TEXT 3053, 0, 0
{
TEXT "$#NAME"
RECT (624,351,656,380)
ALIGN 9
MARGINS (1,1)
PARENT 4987
}
TEXT 3141, 0, 0
{
TEXT "$#NAME"
RECT (1582,1131,1614,1160)
ALIGN 9
MARGINS (1,1)
PARENT 5063
}
TEXT 3145, 0, 0
{
TEXT "$#NAME"
RECT (1024,351,1056,380)
ALIGN 9
MARGINS (1,1)
PARENT 4989
}
NET WIRE 3149, 0, 0
{
VARIABLES
{
#NAME="mr"
}
}
TEXT 3150, 0, 0
{
TEXT "$#NAME"
RECT (645,431,675,460)
ALIGN 9
MARGINS (1,1)
PARENT 4990
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