mips2000.bde

A small MIPS R2000 implementation in VHDL

SCHM0102

HEADER
{
 FREEID 5168
 VARIABLES
 {
  #BLOCKTABLE_FILE="#table.bde"
  #BLOCKTABLE_INCLUDED="1"
  #LANGUAGE="VERILOG"
  #MODULE="mips2000"
  AUTHOR="Gaetano Borriello"
  COMPANY="UW/CSE"
  CREATIONDATE="2/28/2005"
  TITLE="MIPS R2000 for CSE 370 (Winter 2005)"
 }
 SYMBOL "#default" "ALU" "ALU"
 {
  HEADER
  {
   VARIABLES
   {
    #DESCRIPTION=""
    #LANGUAGE="VERILOG"
    #MODIFIED="1109672879"
   }
  }
  PAGE "" 
  {
   PAGEHEADER
   {
    RECT (-20,20,260,320)
    FREEID 35
   }
   
   BODY
   {
    TEXT  3, 4, 0
    {
     TEXT "$#NAME"
     RECT (5,230,88,254)
     ALIGN 4
     MARGINS (1,1)
     PARENT 2
    }
    TEXT  5, 0, 0
    {
     TEXT "$#NAME"
     RECT (120,150,235,174)
     ALIGN 6
     MARGINS (1,1)
     PARENT 4
    }
    TEXT  7, 0, 0
    {
     TEXT "$#NAME"
     RECT (5,90,84,114)
     ALIGN 4
     MARGINS (1,1)
     PARENT 6
    }
    TEXT  9, 0, 0
    {
     TEXT "$#NAME"
     RECT (201,190,235,214)
     ALIGN 6
     MARGINS (1,1)
     PARENT 8
    }
    TEXT  11, 0, 0
    {
     TEXT "$#NAME"
     RECT (5,110,106,134)
     ALIGN 4
     MARGINS (1,1)
     PARENT 10
    }
    TEXT  13, 0, 0
    {
     TEXT "$#NAME"
     RECT (196,110,235,134)
     ALIGN 6
     MARGINS (1,1)
     PARENT 12
    }
    TEXT  15, 2, 0
    {
     TEXT "$#NAME"
     RECT (5,210,106,234)
     ALIGN 4
     MARGINS (1,1)
     PARENT 14
    }
    TEXT  17, 0, 0
    {
     TEXT "$#NAME"
     RECT (137,248,200,272)
     ALIGN 6
     MARGINS (1,1)
     PARENT 16
     ORIENTATION 4
    }
    TEXT  19, 0, 0
    {
     TEXT "$#NAME"
     RECT (60,48,101,72)
     ALIGN 4
     MARGINS (1,1)
     PARENT 18
    }
    TEXT  21, 4, 0
    {
     TEXT "$#NAME"
     RECT (20,268,100,292)
     ALIGN 6
     MARGINS (1,1)
     PARENT 20
     ORIENTATION 4
    }
    RECT  30, 0, 0
    {
     OUTLINE 0,2, (132,4,0)
     AREA (0,200,120,300)
     FILL (0,(255,255,156),0)
    }
    RECT  31, -2, 0
    {
     OUTLINE 0,2, (132,4,0)
     AREA (0,40,120,140)
     FILL (0,(255,255,156),0)
    }
    LINE  32, 0, 0
    {
     OUTLINE 0,2, (128,64,0)
     POINTS ( (140,40), (140,40) )
     FILL (1,(0,0,0),0)
    }
    GROUP  33, -1, 0
    {
     RECT (120,40,239,299)
     VARIABLES
     {
      #NAME="ALU"
      #OUTLINE_FILLING="1"
     }
     FREEID 1
     LINE  24, 0, 0
     {
      OUTLINE 0,2, (132,4,0)
      POINTS ( (58,129), (0,96), (0,0), (118,64), (118,193), (0,258), (0,161), (58,129) )
      FILL (0,(255,255,156),0)
     }
    }
    LINE  34, 0, 0
    {
     OUTLINE 0,3, (0,0,0)
     POINTS ( (160,280), (160,300) )
     FILL (1,(0,0,0),0)
    }
    PIN  2, 4, 0
    {
     COORD (-20,240)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #NAME="Inst(31:0)"
      #NUMBER="0"
      #SIDE="left"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  4, 0, 0
    {
     COORD (260,160)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #NAME="ALUout(31:0)"
      #NUMBER="0"
      #SIDE="right"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  6, 0, 0
    {
     COORD (-20,100)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #NAME="PC(31:0)"
      #NUMBER="0"
      #SIDE="left"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  8, 0, 0
    {
     COORD (260,200)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #NAME="neg"
      #NUMBER="0"
      #SIDE="right"
      #VERILOG_TYPE="reg"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  10, 0, 0
    {
     COORD (-20,120)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #NAME="RegA(31:0)"
      #NUMBER="0"
      #SIDE="left"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  12, 0, 0
    {
     COORD (260,120)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #NAME="zero"
      #NUMBER="0"
      #VERILOG_TYPE="reg"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  14, 4, 0
    {
     COORD (-20,220)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #NAME="RegB(31:0)"
      #NUMBER="0"
      #SIDE="left"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  16, 0, 0
    {
     COORD (160,320)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #NAME="op(5:0)"
      #NUMBER="0"
      #SIDE="bottom"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (0,-20) )
     }
    }
    PIN  18, 0, 0
    {
     COORD (80,20)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #NAME="srcA"
      #NUMBER="0"
      #SIDE="top"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (0,20) )
     }
    }
    PIN  20, 4, 0
    {
     COORD (80,320)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #NAME="srcB(1:0)"
      #NUMBER="0"
      #SIDE="bottom"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (0,-20) )
     }
    }
   }
  }
 }
 SYMBOL "#default" "Controller" "Controller"
 {
  HEADER
  {
   VARIABLES
   {
    #DESCRIPTION=""
    #LANGUAGE="VERILOG"
    #MODIFIED="1109673291"
   }
  }
  PAGE "" 
  {
   PAGEHEADER
   {
    RECT (0,0,240,640)
    FREEID 46
   }
   
   BODY
   {
    RECT  1, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     AREA (20,0,220,640)
    }
    TEXT  3, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,30,108,54)
     ALIGN 4
     MARGINS (1,1)
     PARENT 2
    }
    TEXT  5, 0, 0
    {
     TEXT "$#NAME"
     RECT (124,30,215,54)
     ALIGN 6
     MARGINS (1,1)
     PARENT 4
    }
    TEXT  9, 0, 0
    {
     TEXT "$#NAME"
     RECT (178,70,215,94)
     ALIGN 6
     MARGINS (1,1)
     PARENT 8
    }
    TEXT  11, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,230,59,254)
     ALIGN 4
     MARGINS (1,1)
     PARENT 10
    }
    TEXT  13, 0, 0
    {
     TEXT "$#NAME"
     RECT (156,110,215,134)
     ALIGN 6
     MARGINS (1,1)
     PARENT 12
    }
    TEXT  15, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,410,70,434)
     ALIGN 4
     MARGINS (1,1)
     PARENT 14
    }
    TEXT  17, 0, 0
    {
     TEXT "$#NAME"
     RECT (171,150,215,174)
     ALIGN 6
     MARGINS (1,1)
     PARENT 16
    }
    TEXT  19, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,190,64,214)
     ALIGN 4
     MARGINS (1,1)
     PARENT 18
    }
    TEXT  21, 0, 0
    {
     TEXT "$#NAME"
     RECT (134,190,215,214)
     ALIGN 6
     MARGINS (1,1)
     PARENT 20
    }
    TEXT  23, 0, 0
    {
     TEXT "$#NAME"
     RECT (161,230,215,254)
     ALIGN 6
     MARGINS (1,1)
     PARENT 22
    }
    TEXT  25, 0, 0
    {
     TEXT "$#NAME"
     RECT (111,270,215,294)
     ALIGN 6
     MARGINS (1,1)
     PARENT 24
    }
    TEXT  27, 0, 0
    {
     TEXT "$#NAME"
     RECT (191,310,215,334)
     ALIGN 6
     MARGINS (1,1)
     PARENT 26
    }
    TEXT  29, 0, 0
    {
     TEXT "$#NAME"
     RECT (184,350,215,374)
     ALIGN 6
     MARGINS (1,1)
     PARENT 28
    }
    TEXT  31, 0, 0
    {
     TEXT "$#NAME"
     RECT (152,390,215,414)
     ALIGN 6
     MARGINS (1,1)
     PARENT 30
    }
    TEXT  33, 0, 0
    {
     TEXT "$#NAME"
     RECT (140,430,215,454)
     ALIGN 6
     MARGINS (1,1)
     PARENT 32
    }
    TEXT  35, 0, 0
    {
     TEXT "$#NAME"
     RECT (174,470,215,494)
     ALIGN 6
     MARGINS (1,1)
     PARENT 34
    }
    TEXT  37, 0, 0
    {
     TEXT "$#NAME"
     RECT (135,510,215,534)
     ALIGN 6
     MARGINS (1,1)
     PARENT 36
    }
    TEXT  39, 0, 0
    {
     TEXT "$#NAME"
     RECT (127,550,215,574)
     ALIGN 6
     MARGINS (1,1)
     PARENT 38
    }
    TEXT  41, 0, 0
    {
     TEXT "$#NAME"
     RECT (130,590,215,614)
     ALIGN 6
     MARGINS (1,1)
     PARENT 40
    }
    TEXT  45, 0, 0
    {
     TEXT "$#NAME"
     RECT (40,588,65,612)
     ALIGN 4
     MARGINS (1,1)
     PARENT 44
    }
    PIN  2, 0, 0
    {
     COORD (0,40)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #NAME="Inst(31:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  4, 0, 0
    {
     COORD (240,40)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #NAME="ALUmaEN"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  8, 0, 0
    {
     COORD (240,80)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #NAME="IRld"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  10, 0, 0
    {
     COORD (0,240)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #NAME="neg"
      #NUMBER="0"
      #SIDE="left"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  12, 0, 0
    {
     COORD (240,120)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #NAME="MBRld"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  14, 0, 0
    {
     COORD (0,420)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #NAME="reset"
      #NUMBER="0"
      #SIDE="left"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  16, 0, 0
    {
     COORD (240,160)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #NAME="PCld"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  18, 0, 0
    {
     COORD (0,200)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #NAME="zero"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  20, 0, 0
    {
     COORD (240,200)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #NAME="PCmaEN"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  22, 0, 0
    {
     COORD (240,240)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #NAME="PCsel"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  24, 0, 0
    {
     COORD (240,280)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #NAME="RegBmdEN"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  26, 0, 0
    {
     COORD (240,320)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #NAME="mr"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  28, 0, 0
    {
     COORD (240,360)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #NAME="mw"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  30, 0, 0
    {
     COORD (240,400)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #NAME="op(5:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  32, 0, 0
    {
     COORD (240,440)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #NAME="regWrite"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  34, 0, 0
    {
     COORD (240,480)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #NAME="srcA"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  36, 0, 0
    {
     COORD (240,520)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #NAME="srcB(1:0)"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  38, 0, 0
    {
     COORD (240,560)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #NAME="wrDataSel"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  40, 0, 0
    {
     COORD (240,600)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #NAME="wrRegSel"
      #NUMBER="0"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  44, 0, 0
    {
     COORD (0,600)
     VARIABLES
     {
      #DIRECTION="IN"
      #LABEL="CLK"
      #LENGTH="20"
      #MODIFIED=""
      #NAME="clk"
      #NUMBER="1"
      #SIDE="left"
     }
     LINE  1, 0, 0
     {
      OUTLINE 0,1, (0,0,128)
      POINTS ( (0,0), (20,0) )
     }
     LINE  2, 0, 0
     {
      OUTLINE 0,1, (0,0,128)
      POINTS ( (20,0), (20,-10), (30,0), (20,10), (20,0) )
     }
    }
   }
  }
 }
 SYMBOL "#default" "Memory" "Memory"
 {
  HEADER
  {
   VARIABLES
   {
    #DESCRIPTION=""
    #GENERIC0="ALU:integer:=6'h0"
    #GENERIC1="LW:integer:=6'h23"
    #GENERIC10="r2:integer:=5'h02"
    #GENERIC11="r3:integer:=5'h03"
    #GENERIC12="rz:integer:=5'h1f"
    #GENERIC13="ADD:integer:=6'h20"
    #GENERIC14="SUB:integer:=6'h22"
    #GENERIC15="AND:integer:=6'h24"
    #GENERIC16="OR:integer:=6'h25"
    #GENERIC17="SLT:integer:=6'h2a"
    #GENERIC2="SW:integer:=6'h2b"
    #GENERIC3="BEQ:integer:=6'h04"
    #GENERIC4="ADDI:integer:=6'h08"
    #GENERIC5="J:integer:=6'h02"
    #GENERIC6="HALT:integer:=6'h3f"
    #GENERIC7="shftX:integer:=5'hx"
    #GENERIC8="r0:integer:=5'h0"
    #GENERIC9="r1:integer:=5'h01"
    #LANGUAGE="VERILOG"
    #MODIFIED="1109670765"
   }
  }
  PAGE "" 
  {
   PAGEHEADER
   {
    RECT (0,0,300,120)
    FREEID 10
   }
   
   BODY
   {
    RECT  1, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     AREA (20,20,300,100)
    }
    TEXT  3, 0, 0
    {
     TEXT "$#NAME"
     RECT (99,68,220,92)
     ALIGN 6
     MARGINS (1,1)
     PARENT 2
     ORIENTATION 4
    }
    TEXT  5, 0, 0
    {
     TEXT "$#NAME"
     RECT (120,28,208,52)
     ALIGN 4
     MARGINS (1,1)
     PARENT 4
     ORIENTATION 2
    }
    TEXT  7, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,30,65,54)
     ALIGN 4
     MARGINS (1,1)
     PARENT 6
    }
    TEXT  9, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,70,66,94)
     ALIGN 4
     MARGINS (1,1)
     PARENT 8
    }
    PIN  2, 0, 0
    {
     COORD (160,120)
     VARIABLES
     {
      #DIRECTION="IN"
      #DOWNTO="1"
      #LENGTH="20"
      #NAME="address(31:0)"
      #NUMBER="0"
      #SIDE="bottom"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (0,-20) )
     }
    }
    PIN  4, 0, 0
    {
     COORD (160,0)
     VARIABLES
     {
      #DIRECTION="INOUT"
      #DOWNTO="1"
      #LENGTH="20"
      #NAME="data(31:0)"
      #NUMBER="0"
      #SIDE="top"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,20), (0,0) )
     }
    }
    PIN  6, 0, 0
    {
     COORD (0,40)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #NAME="read"
      #NUMBER="0"
      #SIDE="left"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }