clock.cdf

来自「用Verilog HDL 实现时钟(时和分)」· CDF 代码 · 共 14 行

/* Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version */
JedecChain;
	FileRevision(JESD32A);
	DefaultMfr(6E);

	P ActionCode(Cfg)
		Device PartName(EPM240T100) Path("F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/") File("clock.pof") MfrSpec(OpMask(7) SEC_Device(EPM240T100) Child_OpMask(2 7 7));

ChainEnd;

AlteraBegin;
	ChainType(JTAG);
AlteraEnd;