clock.fit.summary

来自「用Verilog HDL 实现时钟(时和分)」· SUMMARY 代码 · 共 12 行

Fitter Status : Successful - Tue Jan 20 14:10:12 2009
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : clock
Top-level Entity Name : clock
Family : MAX II
Device : EPM240T100C5
Timing Models : Final
Total logic elements : 99 / 240 ( 41 % )
Total pins : 16 / 80 ( 20 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )