tb_top_ram.v

这是我做的一个BCH译码模块硬件语言模块

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   09:28:49 12/14/2006
// Design Name:   top_ram
// Module Name:   tb_top_ram.v
// Project Name:  bch_dec
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: top_ram
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_top_ram_v;

	// Inputs
	reg clk;
	reg reset;
	reg [29:0] word;
	reg [3:0] word_cnt;
	reg en_word;
	reg clk_rd;
	reg [4:0] addr_rd;
	reg en_rd;

	// Outputs
	wire [14:0] data_rd;
	wire full_flag;

	// Instantiate the Unit Under Test (UUT)
	top_ram uut (
		.clk(clk), 
		.reset(reset), 
		.word(word), 
		.word_cnt(word_cnt), 
		.en_word(en_word), 
		.clk_rd(clk_rd), 
		.addr_rd(addr_rd), 
		.en_rd(en_rd), 
		.data_rd(data_rd), 
		.full_flag(full_flag)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 0;
		word = 0;
		word_cnt = 0;
		en_word = 0;
		clk_rd = 0;
		addr_rd = 0;
		en_rd = 0;

		// Wait 100 ns for global reset to finish
	
			#5 reset=1;
				#25  			//1100_1100_110_0011_1010_1010_101_1011	第一个字正确
					  word=30'b1101_1100_110_0011_0010_1010_101_1011;	//当为第一个字
					  			//1100_1100_110_1010_1010_101_0011_1011	其他字正确
					  //word=30'b1100_1101_110_1010_1010_101_0011_1010;	//其他字	 1
				     word_cnt=4'b0000;
					  en_word=1;
				#20  en_word=0;
				#600 	word=30'b1100_1101_110_1010_1010_101_0011_1010;
					    word_cnt=4'b0001;
						 en_word=1;
				#20    en_word=0;
				#600	  word=30'b1100_1101_110_1010_1110_101_0011_1011;	//其他字	
				       word_cnt=4'b0010;
					    en_word=1;
				#20  en_word=0;
				#600 	word=30'b1000_1100_110_1010_1010_101_0011_0011;
					    word_cnt=4'b0011;
						 en_word=1;
				#20    en_word=0;
				#600	  word=30'b1101_1100_110_1010_1110_101_0011_1011;	//其他字
				       word_cnt=4'b0100;
					    en_word=1;
				#20  en_word=0;
					#600 	word=30'b0100_1100_110_1010_1010_101_0011_1011;
					    word_cnt=4'b0101;
						 en_word=1;
				#20    en_word=0;
				#600	  word=30'b1100_1101_110_1010_1110_101_0011_1011;	//其他字
				       word_cnt=4'b0110;
					    en_word=1;
				#20  en_word=0;
				#600 	word=30'b1100_1100_110_1010_1011_101_0011_1011;
					    word_cnt=4'b0111;
						 en_word=1;
				#20    en_word=0;
				#600	  word=30'b1100_1101_110_1010_1110_101_0011_1011;	//其他字
				       word_cnt=4'b1000;
					    en_word=1;
				#20  en_word=0;
					#600 	word=30'b1100_1100_110_1010_1010_101_0011_1011;
					    word_cnt=4'b1001;
						 en_word=1;
				#20    en_word=0;
			
			
        
		// Add stimulus here

	end
 always #10 clk=~clk;     
endmodule