tb_bch_top.v

来自「这是我做的一个BCH译码模块硬件语言模块」· Verilog 代码 · 共 73 行

  `timescale 1ns/1ps
module bch_top_tb_bch_top_v_tf();

// DATE:     14:21:00 12/06/2006 
// MODULE:   bch_top
// DESIGN:   bch_top
// FILENAME: tb_bch_top.v
// PROJECT:  bch_decode
// VERSION:  


// Inputs
    reg clk;
    reg reset;
    reg [29:0] word;
    reg [3:0] word_cnt;
    reg en_word;


// Outputs
    wire [29:0] word_dec;
    wire en_word_dec;


// Bidirs


// Instantiate the UUT
    bch_top uut (
        .clk(clk), 
        .reset(reset), 
        .word(word), 
        .word_cnt(word_cnt), 
        .en_word(en_word), 
        .word_dec(word_dec), 
        .en_word_dec(en_word_dec)
        );


// Initialize Inputs
   

        initial begin
            clk = 0;
            reset = 0;
            word = 0;
            word_cnt = 0;
            en_word = 0;
				#5 reset=1;
				#25  			//1100_1100_110_0011_1010_1010_101_1011	第一个字正确
					  //word=30'b1101_1100_110_0011_0010_1010_101_1011;	//当为第一个字
					  			//1100_1100_110_1010_1010_101_0011_1011	其他字正确
					  word=30'b1100_1101_110_1010_1010_101_0011_1010;	//其他字
				     word_cnt=4'b0010;
					  en_word=1;
				#20  en_word=0;
				#600 	word=30'b1101_1100_110_0011_1010_1010_100_1011;
					    word_cnt=4'b0000;
						 en_word=1;
				#20    en_word=0;
				#600	  word=30'b1100_1101_110_1010_1110_101_0011_1011;	//其他字
				       word_cnt=4'b0100;
					    en_word=1;
				#20  en_word=0;
        end

  always #10 clk=~clk;


endmodule