bch_top.v

来自「这是我做的一个BCH译码模块硬件语言模块」· Verilog 代码 · 共 36 行

module bch_top(clk,reset,word,word_cnt,en_word,word_dec,en_word_dec);
    input [0:0] clk;
    input [0:0] reset;
    input [29:0] word;
    input [3:0] word_cnt;
    input [0:0] en_word;
    output [29:0] word_dec;
    output [0:0] en_word_dec;

	 wire [29:0] word_wire;
	 wire gate_ctr;
	 wire word_en_d1;
	 

	 input_ctr u_ctr (.clk(clk),
	                  .rst(reset),
	                  .word_cnt(word_cnt),
	                  .word_in(word),
	                  .word_out(word_wire),
	                  .gate_ctr(gate_ctr),
							.word_en_d1(word_en_d1),
	                  .word_en(en_word));

	  module_dec u_module_dec (.clk(clk),
	                           .rst(reset),
	                           .gate(gate_ctr),
	                           .word(word_wire),
	                           .word_en(word_en_d1),
										.word_cnt(word_cnt),
	                           .data_out(word_dec),
	                           .en_word_dec(en_word_dec));



endmodule