tb_modul.v

来自「这是我做的一个BCH译码模块硬件语言模块」· Verilog 代码 · 共 62 行

module module_dec_tb_modul_v_tf();

// DATE:     15:54:01 12/05/2006 
// MODULE:   module_dec
// DESIGN:   module_dec
// FILENAME: tb_modul.v
// PROJECT:  bch_decode
// VERSION:  


// Inputs
    reg clk;
    reg rst;
    reg gate;
    reg [29:0] word;
    reg word_en;


// Outputs
    wire [29:0] data_out;
   
	 wire en_word_dec;

// Bidirs


// Instantiate the UUT
    module_dec uut (
        .clk(clk), 
        .rst(rst), 
        .gate(gate), 
        .word(word), 
        .word_en(word_en), 
        .data_out(data_out),
        .en_word_dec(en_word_dec)
        );


// Initialize Inputs
 

        initial begin
            clk = 0;
            rst = 0;
            gate = 1;
            word = 0;
            word_en = 0;
			 #5 gate=1;
			    rst=1;
			 #25  word=30'b110011001111100_110011001001100 ;
			      word_en=1;
			  #20 word_en=0;
        end

 always #10 clk=~clk;


endmodule