top_ram.v

这是我做的一个BCH译码模块硬件语言模块

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    16:44:49 12/12/06
// Design Name:    
// Module Name:    top_ram
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module top_ram(clk, reset, word, word_cnt, en_word, clk_rd,addr_rd, en_rd, data_rd,full_flag);
    input [0:0] clk;
    input [0:0] reset;
    input [29:0] word;
    input [3:0] word_cnt;
    input [0:0] en_word;
    input [4:0] addr_rd;
    input [0:0] en_rd;
	 input [0:0] clk_rd;
    output [14:0] data_rd;
	 output [0:0] full_flag;

	 wire [29:0] word_dec;
	 wire [0:0]	 en_word_dec;
	 wire [14:0] data_wr;
	 wire	[4:0]	 addr_wr;
	 wire en_wr;

  bch_top  u_bch_top (.clk(clk),.reset(reset),.word(word),.word_cnt(word_cnt),
                      .en_word(en_word),.word_dec(word_dec),.en_word_dec(en_word_dec));
  
  ram_ctr u_ram_ctr (.clk(clk), .rst(reset), .data_in(word_dec), .data_en(en_word_dec),
                     .data_wr(data_wr), .addr_wr(addr_wr), .en_wr(en_wr),.full_flag(full_flag));
  
  ram20x15 u_ram20x15 (.addra(addr_wr),.dina(data_wr),.wea(en_wr),.clka(clk),
                       .addrb(addr_rd),.clkb(clk_rd),.doutb(data_rd),.enb(en_rd),.sinitb());
endmodule