input_ctr.v

这是我做的一个BCH译码模块硬件语言模块

module input_ctr(clk,rst,word_cnt,word_in,word_out,gate_ctr,word_en,word_en_d1);
    input [0:0] clk;
    input [0:0] rst;
    input [3:0] word_cnt;
    input [29:0] word_in;
    input [0:0] word_en;
	 output word_en_d1;

	 output [29:0] word_out;
    output [0:0] gate_ctr;

	 reg d;

	 reg gate_reg;
	
	 wire gate_off;
	 assign word_en_d1=d;
	 assign  word_out=(word_cnt==4'b0000) ? {word_in[29:15],word_in[14:0]} 
	                  : {word_in[29:19],word_in[7:4],word_in[18:8],word_in[3:0]}	;
	 
	 assign gate_ctr=gate_reg;


	 word_en_ctr u_word_en (.clk(clk),
	                        .rst(rst),
	                        .word_en(word_en),
	                        .d1(),
									.d15(),
	                        .d16(gate_off),
	                        .d17(),
	                        .d18(),
	                        .d19(),
	                        .d31(),
	                        .d32(),
	                        .d33(),
	                        .d34(),
									.d35(),
									.d36(),
	                        .start());
	always @(posedge clk or negedge rst)					//产生门信号
	     begin 
		     if(!rst)
			      gate_reg<=1;
			  else if(word_cnt==4'b0000)
			       begin
			             if (word_en)
			                  gate_reg<=0;
			             else if(gate_off)
			                  gate_reg<=1;
					 end
			end

		always @(posedge clk or negedge rst)
			 begin 
		     if(!rst)
			  d<=0;
			  else
			  d<=word_en;
			 end

endmodule