module_dec.v

这是我做的一个BCH译码模块硬件语言模块

module module_dec(clk,rst,gate,word,word_en,word_cnt,data_out,en_word_dec);
    input [0:0] clk;
    input [0:0] rst;
    input [0:0] gate;
    input [29:0] word;											  //输入字
    input [0:0] word_en;
	 input [3:0] word_cnt;										  //输入使能
  
	 output en_word_dec;
    output [29:0] data_out;

	 wire d1,d15,d16,d17,d18,d19,d31,d32,d33,d34,d35,d36,start;				 //控制信号
	 wire signal;																//串行输入
	 wire [3:0]	in_lookup;												  //查找表输入
	 wire [14:0] out_lookup;

	 assign en_word_dec=d36;
	 word_en_ctr u_logic_ctr(.clk(clk),							  //控制信号模块
	                         .rst(rst),
	                         .word_en(word_en),
	                         .d1(d1),
									 .d15(d15),
	                         .d16(d16),
	                         .d17(d17),
	                         .d18(d18),
	                         .d19(d19),
	                         .d31(d31),
	                         .d32(d32),
	                         .d33(d33),
	                         .d34(d34),
									 .d35(d35),
	                         .d36(d36),
	                         .start(start));

	  par_ser u_par_ser(.clk(clk),.rst(rst),.word(word),				 //并串转换
	                    .word_en(word_en),.word_en_start(start),
	                    .data_out(signal));

	  bch_divd u_bch (.clk(clk),.rst(rst),.gate(gate),.d16(d16),			  //bch码移位除法
	                  .d31(d31),.start(start),.in(signal),.data_out(in_lookup));

	  lookup_ero u_lookup (.clk(clk),.rst(rst),.in(in_lookup),.data_out(out_lookup));	//查找表

	  model_2  u_mode (.clk(clk),.rst(rst),.start(start),.signal_in(signal),.word_cnt(word_cnt),				 //模2加
	                   .data_in(out_lookup),.d16(d16),.d18(d18),.d31(d31),.d33(d33),.d35(d35)	,
				          .data_out(data_out));

endmodule