ram_ctr.v

这是我做的一个BCH译码模块硬件语言模块

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    15:42:06 12/12/06
// Design Name:    
// Module Name:    ram_ctr
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module ram_ctr(clk, rst, data_in, data_en, data_wr, addr_wr, en_wr,full_flag);
    input [0:0] clk;
    input [0:0] rst;
    input [29:0] data_in;
    input [0:0] data_en;
    output [14:0] data_wr;
    output [4:0] addr_wr;
    output [0:0] en_wr;
	 output       full_flag;

    reg  [0:0]	delay_reg1;
	 reg  [0:0]	delay_reg2;

	 reg [4:0] addr_cnt;
	
	 reg  [14:0] data_wr;
	 reg  [4:0]addr_wr;
	 reg  full_flag;
	 assign en_wr=delay_reg1 | delay_reg2  ;
	 always @(posedge clk or negedge rst)
	     begin
		     if(!rst)
			     delay_reg1<=0;
			  else 
			      delay_reg1<=data_en;
			end
    always @(posedge clk or negedge rst)
	     begin
		     if(!rst)
			     delay_reg2<=0;
			  else 
			      delay_reg2<=delay_reg1;
			end
  

	  always @(posedge clk or negedge rst)
	      begin
			   if(!rst)
				 begin
				  addr_cnt<=0;
				  full_flag<=0;
				  end
				else if(data_en)
				  begin
				     data_wr<=data_in[29:15];
					  addr_wr<=addr_cnt;
					 
					  addr_cnt<=addr_cnt+1;
				   end
				else if(delay_reg1)
				   begin
					  data_wr<=data_in[14:0];
					  addr_wr<=addr_cnt;
					 
					  addr_cnt<=addr_cnt+1;
					end
				else if(addr_cnt==5'b10100)
				   begin
					   addr_cnt<=0;
						full_flag<=1;
					end
				else
				     full_flag<=0;
			end		    

endmodule