assert_quiescent_state_logic.sv

来自「OVL——基于断言的verilog验证 Verilog数字系统设计:RTL综合」· SV 代码 · 共 43 行

// Accellera Standard V1.0 Open Verification Library (OVL).
// Accellera Copyright (c) 2005. All rights reserved.

  parameter assert_name = "ASSERT_QUIESCENT_STATE";

  `include "std_ovl_task.h"

  `ifdef OVL_INIT_MSG
    initial
      ovl_init_msg_t; // Call the User Defined Init Message Routine
  `endif

  `ifdef OVL_END_OF_SIMULATION
    property ASSERT_QUIESCENT_STATE_P;
    @(posedge clk)
    disable iff (`OVL_RESET_SIGNAL != 1'b1)
    ($rose(`OVL_END_OF_SIMULATION) || $rose(sample_event)) |-> (state_expr == check_value);
    endproperty
  `else
    property ASSERT_QUIESCENT_STATE_P;
    @(posedge clk)
    disable iff (`OVL_RESET_SIGNAL != 1'b1)
    $rose(sample_event) |-> (state_expr == check_value);
    endproperty
  `endif // OVL_END_OF_SIMULATION

`ifdef OVL_ASSERT_ON

  generate

    case (property_type)
      `OVL_ASSERT : A_ASSERT_QUIESCENT_STATE_P:
                    assert property (ASSERT_QUIESCENT_STATE_P)
                    else ovl_error_t("");
      `OVL_ASSUME : M_ASSERT_QUIESCENT_STATE_P:
                    assume property (ASSERT_QUIESCENT_STATE_P);
      default     : ovl_error_t("");
    endcase

  endgenerate

`endif // OVL_ASSERT_ON