assert_always_on_edge_logic.v

来自「OVL——基于断言的verilog验证 Verilog数字系统设计:RTL综合」· Verilog 代码 · 共 36 行

// Accellera Standard V1.0 Open Verification Library (OVL).
// Accellera Copyright (c) 2005. All rights reserved.

  parameter assert_name = "ASSERT_ALWAYS_ON_EDGE";

  `include "std_ovl_task.h"
  
  `ifdef OVL_INIT_MSG
    initial
      ovl_init_msg_t; // Call the User Defined Init Message Routine
  `endif

`ifdef OVL_ASSERT_ON

  reg sampling_event_prev;

  always @(posedge clk) begin
    if (`OVL_RESET_SIGNAL != 1'b0) begin
// Capture Sampling Event @Clock for rising edge detections
      sampling_event_prev <= sampling_event; 
      if ((edge_type == `OVL_NOEDGE) && (!test_expr))
        ovl_error_t("");
      else if ((edge_type == `OVL_POSEDGE) && (!sampling_event_prev) && 
	      (sampling_event) && (!test_expr))
        ovl_error_t("");
      else if ((edge_type == `OVL_NEGEDGE) && (sampling_event_prev) && 
		(!sampling_event) && (!test_expr))
        ovl_error_t("");
	else if ((edge_type == `OVL_ANYEDGE) && 
		(sampling_event_prev != sampling_event) && (!test_expr))
	  ovl_error_t("");
	end
    end

`endif // OVL_ASSERT_ON