assert_transition_logic.sv

来自「OVL——基于断言的verilog验证 Verilog数字系统设计:RTL综合」· SV 代码 · 共 52 行

// Accellera Standard V1.0 Open Verification Library (OVL).
// Accellera Copyright (c) 2005. All rights reserved.

  parameter assert_name = "ASSERT_TRANSITION";

  `include "std_ovl_task.h"

  `ifdef OVL_INIT_MSG
    initial
      ovl_init_msg_t; // Call the User Defined Init Message Routine
  `endif

  property ASSERT_TRANSITION_P;
  @(posedge clk)
  disable iff (`OVL_RESET_SIGNAL != 1'b1)
  (test_expr == start_state) |=> ( (test_expr == $past(start_state)) ||
                                   (test_expr == $past(next_state)) );
  endproperty

`ifdef OVL_ASSERT_ON

  generate

    case (property_type)
      `OVL_ASSERT : A_ASSERT_TRANSITION_P:
                    assert property (ASSERT_TRANSITION_P) else ovl_error_t("");
      `OVL_ASSUME : M_ASSERT_TRANSITION_P: 
                    assume property (ASSERT_TRANSITION_P);
      default     : ovl_error_t("");
    endcase

  endgenerate

`endif // OVL_ASSERT_ON

`ifdef OVL_COVER_ON

generate

 if (coverage_level != `OVL_COVER_NONE) begin

  cover_start_state:
  cover property (@(posedge clk) ( (`OVL_RESET_SIGNAL != 1'b0) &&
                                   (test_expr == start_state)) )
                 ovl_cover_t("start_state covered");

 end

endgenerate

`endif // OVL_COVER_ON