assert_implication.vlib

来自「OVL——基于断言的verilog验证 Verilog数字系统设计:RTL综合」· VLIB 代码 · 共 22 行

// Accellera Standard V1.0 Open Verification Library (OVL).
// Accellera Copyright (c) 2005. All rights reserved.

`include "std_ovl_defines.h"

`module assert_implication (clk, reset_n, antecedent_expr, consequent_expr);
  input clk, reset_n, antecedent_expr, consequent_expr;
  parameter severity_level = `OVL_ERROR;
  parameter property_type = `OVL_ASSERT;
  parameter msg="VIOLATION";
  parameter coverage_level = `OVL_COVER_ALL;

`ifdef OVL_VERILOG
  `include "./vlog95/assert_implication_logic.v"
`endif // OVL_VERILOG

`ifdef OVL_SVA
  `include "./sva31a/assert_implication_logic.sv"
`endif // OVL_SVA

`endmodule