assert_never_logic.v

来自「OVL——基于断言的verilog验证 Verilog数字系统设计:RTL综合」· Verilog 代码 · 共 33 行

// Accellera Standard V1.0 Open Verification Library (OVL).
// Accellera Copyright (c) 2005. All rights reserved.

  parameter assert_name = "ASSERT_NEVER";

  `include "std_ovl_task.h"

  `ifdef OVL_INIT_MSG
    initial
      ovl_init_msg_t; // Call the User Defined Init Message Routine
  `endif

`ifdef OVL_ASSERT_ON

 always @(posedge clk) begin
      if (`OVL_RESET_SIGNAL != 1'b0) begin // active low reset
        if ((test_expr ^ test_expr)==0) begin
          if (test_expr == 1'b1) begin
            ovl_error_t("");
          end
        end
        else begin
          `ifdef OVL_XCHECK_OFF
          // do nothing
          `else
          ovl_error_t("test_expr contains X/Z value");
          `endif // OVL_XCHECK_OFF
        end
      end
  end // always

`endif // OVL_ASSERT_ON