shift.vhd

来自「本设计是一个八位被除数除以四位除数」· VHDL 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shift is
	port(shifted:in std_logic_vector(8 downto 0);
		sh_en:in std_logic;
		load:in std_logic;
		c:in std_logic;
		differ:out std_logic_vector(8 downto 0));
	end shift;
architecture behav of shift is
signal shiftin:std_logic_vector(8 downto 0);
begin
   sh_perform:process(shifted,sh_en,c)
	begin
	if load='1' then shiftin<=shifted;
	elsif rising_edge(sh_en) then
		shiftin(0)<=c;
		shiftin(1)<=shifted(0);
		shiftin(2)<=shifted(1);
		shiftin(3)<=shifted(2);
		shiftin(4)<=shifted(3);
		shiftin(5)<=shifted(4);
		shiftin(6)<=shifted(5);
		shiftin(7)<=shifted(6);
		shiftin(8)<=shifted(7);	
	end if;
	end process sh_perform;
	differ<=shiftin;
end behav;