srg4.vhd

来自「本设计是一个八位被除数除以四位除数」· VHDL 代码 · 共 20 行

library ieee;
use ieee.std_logic_1164.all;
entity srg4 is
port(clk:in std_logic;
	input:in std_logic;
	diag,su_en,sh_en,update:out std_logic);
end srg4;
architecture behav of srg4 is
signal srg_4:std_logic_vector(2 downto 0):="000";
begin
process(clk,input,srg_4)
begin
if clk'event and clk='1' then
srg_4(0)<=srg_4(1);
srg_4(1)<=srg_4(2);
srg_4(2)<=input;
end if;
end process;
diag<=srg_4(2);su_en<=srg_4(1);sh_en<=srg_4(0);update<=srg_4(1);
end behav;