sub_5.vhd

来自「本设计是一个八位被除数除以四位除数」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sub_5 is
	port(minuend:in std_logic_vector(4 downto 0);
		subtrahend:in std_logic_vector(4 downto 0);
		su_en:in std_logic;
		c:in std_logic;
		differ:out std_logic_vector(4 downto 0));
	end sub_5;
architecture behav of sub_5 is
signal differin:std_logic_vector(4 downto 0);
begin
   su_perform:process(minuend,subtrahend,su_en,c)
	begin
	if su_en'event and su_en='1' then
		if c='1' then differin<=minuend-subtrahend;
		else differin<=minuend; end if;
	end if;
	end process su_perform;
	differ<=differin;
end behav;