📄 dividend4.fit.rpt
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; 12 - 13 ; 0 ;
; 14 - 15 ; 0 ;
; 16 - 17 ; 0 ;
; 18 - 19 ; 2 ;
+----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 4.63) ; Number of LABs (Total = 3) ;
+----------------------------------------+-----------------------------+
; 0 ; 5 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 2 ;
+----------------------------------------+-----------------------------+
+---------------------------------------------------------+
; Parallel Expander ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
+--------------------------+------------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 0.75) ; Number of LABs (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 7 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
+-------------------------------------------------+-----------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC13 ; clk, state_graph:u5|srg4:u1|srg_4[1], state_graph:u5|state[1], state_graph:u5|state[2], state_graph:u5|state[0], diag_c:u2|c, st, state_graph:u5|input ; state_graph:u5|input, state_graph:u5|srg4:u1|srg_4[2] ;
; A ; LC14 ; clk, state_graph:u5|input ; state_graph:u5|srg4:u1|srg_4[1], diag_c:u2|c ;
; A ; LC7 ; clk, state_graph:u5|srg4:u1|srg_4[2] ; state_graph:u5|input, state_graph:u5|srg4:u1|srg_4[0], state_graph:u5|state[1], state_graph:u5|state[2], state_graph:u5|state[0], state_graph:u5|isover, sub_5:u3|differin[0], sub_5:u3|differin[1], sub_5:u3|differin[2], sub_5:u3|differin[3] ;
; A ; LC4 ; divisor[2], shift:u4|shiftin[6], divisor[3], shift:u4|shiftin[7], diag_c:u2|c ; sub_5:u3|differin~80 ;
; A ; LC9 ; clk, diag_c:u2|c, state_graph:u5|state[2], state_graph:u5|state[0], state_graph:u5|srg4:u1|srg_4[1], state_graph:u5|state[1] ; state_graph:u5|input, state_graph:u5|state[1], state_graph:u5|state[2], state_graph:u5|state[0], state_graph:u5|load, state_graph:u5|isover, state_graph:u5|overflow ;
; A ; LC15 ; divisor[0], shift:u4|shiftin[4], diag_c:u2|c, state_graph:u5|srg4:u1|srg_4[1] ; remainder[0]~reg0, shift:u4|shiftin[5] ;
; A ; LC11 ; clk, st, state_graph:u5|state[2], state_graph:u5|state[1], state_graph:u5|state[0], state_graph:u5|srg4:u1|srg_4[1], diag_c:u2|c ; state_graph:u5|input, state_graph:u5|state[1], state_graph:u5|state[2], state_graph:u5|state[0], state_graph:u5|load, state_graph:u5|isover, state_graph:u5|overflow ;
; A ; LC10 ; clk, state_graph:u5|state[0], state_graph:u5|state[2], state_graph:u5|state[1], st, state_graph:u5|load ; state_graph:u5|load, shift:u4|shiftin[1], shift:u4|shiftin[2], shift:u4|shiftin[3], shift:u4|shiftin[4], shift:u4|shiftin[5], shift:u4|shiftin[6], shift:u4|shiftin[7], shift:u4|shiftin[8], shift:u4|shiftin[0] ;
; A ; LC5 ; sub_5:u3|differin~75, diag_c:u2|c, shift:u4|shiftin[7], sub_5:u3|differin~57, shift:u4|shiftin[5], divisor[1], divisor[3], sub_5:u3|differin~58, sub_5:u3|differin~54 ; sub_5:u3|differin[3] ;
; A ; LC16 ; shift:u4|shiftin[4], divisor[0], divisor[1], diag_c:u2|c, shift:u4|shiftin[5], state_graph:u5|srg4:u1|srg_4[1] ; remainder[1]~reg0, shift:u4|shiftin[6] ;
; A ; LC3 ; sub_5:u3|differin~69, shift:u4|shiftin[5], divisor[0], divisor[2], diag_c:u2|c, shift:u4|shiftin[4], divisor[1], shift:u4|shiftin[6], state_graph:u5|srg4:u1|srg_4[1] ; remainder[2]~reg0, shift:u4|shiftin[7] ;
; A ; LC6 ; sub_5:u3|differin~80, sub_5:u3|differin~58, sub_5:u3|differin~55, divisor[1], divisor[3], shift:u4|shiftin[7], diag_c:u2|c, sub_5:u3|differin~57, sub_5:u3|differin~56, shift:u4|shiftin[4], divisor[0], state_graph:u5|srg4:u1|srg_4[1] ; remainder[3]~reg0, shift:u4|shiftin[8] ;
; A ; LC12 ; shift:u4|shiftin[7], shift:u4|shiftin[8], divisor[3], diag_c:u2|LessThan0~369, shift:u4|shiftin[6], divisor[2], sub_5:u3|differin~57, shift:u4|shiftin[5], divisor[1], sub_5:u3|differin~56, shift:u4|shiftin[4], divisor[0], state_graph:u5|srg4:u1|srg_4[2] ; state_graph:u5|input, state_graph:u5|state[1], state_graph:u5|state[0], sub_5:u3|differin[0], sub_5:u3|differin[1], sub_5:u3|differin[2], sub_5:u3|differin[3], shift:u4|shiftin[0], state_graph:u5|overflow, sub_5:u3|differin~67, sub_5:u3|differin~69, sub_5:u3|differin~75, sub_5:u3|differin~80 ;
; A ; LC8 ; clk, state_graph:u5|state[0], state_graph:u5|state[1], diag_c:u2|c, state_graph:u5|state[2], state_graph:u5|overflow ; state_graph:u5|overflow, overflow ;
; A ; LC1 ; shift:u4|shiftin[6], diag_c:u2|c ; sub_5:u3|differin~69 ;
; A ; LC2 ; sub_5:u3|differin~67, shift:u4|shiftin[5], shift:u4|shiftin[4], divisor[0], divisor[2], diag_c:u2|c, divisor[1] ; sub_5:u3|differin[2] ;
; B ; LC18 ; state_graph:u5|load, dividend_in[0], shift:u4|shiftin[0], state_graph:u5|srg4:u1|srg_4[0], dividend_in[1] ; quotient[1]~reg0, shift:u4|shiftin[2] ;
; B ; LC22 ; state_graph:u5|load, dividend_in[1], shift:u4|shiftin[1], state_graph:u5|srg4:u1|srg_4[0], dividend_in[2] ; quotient[2]~reg0, shift:u4|shiftin[3] ;
; B ; LC25 ; clk, shift:u4|shiftin[2] ; quotient[2] ;
; B ; LC23 ; state_graph:u5|load, dividend_in[2], shift:u4|shiftin[2], state_graph:u5|srg4:u1|srg_4[0], dividend_in[3] ; quotient[3]~reg0, shift:u4|shiftin[4] ;
; B ; LC27 ; clk, shift:u4|shiftin[3] ; quotient[3] ;
; B ; LC26 ; state_graph:u5|load, dividend_in[3], shift:u4|shiftin[3], state_graph:u5|srg4:u1|srg_4[0], dividend_in[4] ; sub_5:u3|differin[0], sub_5:u3|differin[1], sub_5:u3|differin[2], sub_5:u3|differin~54, sub_5:u3|differin~55, sub_5:u3|differin[3], diag_c:u2|c, sub_5:u3|differin~69 ;
; B ; LC29 ; clk, sub_5:u3|differin[3] ; remainder[3] ;
; B ; LC32 ; state_graph:u5|load, dividend_in[7], sub_5:u3|differin[3], state_graph:u5|srg4:u1|srg_4[0] ; diag_c:u2|c ;
; B ; LC30 ; state_graph:u5|load, dividend_in[5], sub_5:u3|differin[1], state_graph:u5|srg4:u1|srg_4[0], dividend_in[6] ; sub_5:u3|differin[2], sub_5:u3|differin~57, sub_5:u3|differin~58, diag_c:u2|c, sub_5:u3|differin~67, sub_5:u3|differin~75 ;
; B ; LC20 ; diag_c:u2|c, state_graph:u5|srg4:u1|srg_4[0], state_graph:u5|load, dividend_in[0] ; shift:u4|shiftin[1], quotient[0]~reg0 ;
; B ; LC24 ; clk, shift:u4|shiftin[0] ; quotient[0] ;
; B ; LC28 ; state_graph:u5|load, dividend_in[4], sub_5:u3|differin[0], state_graph:u5|srg4:u1|srg_4[0], dividend_in[5] ; sub_5:u3|differin[1], sub_5:u3|differin[2], sub_5:u3|differin~56, diag_c:u2|c, sub_5:u3|differin~69, sub_5:u3|differin~80 ;
; B ; LC19 ; clk, sub_5:u3|differin[2] ; remainder[2] ;
; B ; LC31 ; state_graph:u5|load, dividend_in[6], sub_5:u3|differin[2], state_graph:u5|srg4:u1|srg_4[0], dividend_in[7] ; sub_5:u3|differin[3], diag_c:u2|LessThan0~369, diag_c:u2|c, sub_5:u3|differin~75, sub_5:u3|differin~80 ;
; B ; LC17 ; clk, sub_5:u3|differin[1] ; remainder[1] ;
; B ; LC21 ; clk, sub_5:u3|differin[0] ; remainder[0] ;
; C ; LC34 ; clk, state_graph:u5|srg4:u1|srg_4[1] ; shift:u4|shiftin[1], shift:u4|shiftin[2], shift:u4|shiftin[3], shift:u4|shiftin[4], shift:u4|shiftin[5], shift:u4|shiftin[6], shift:u4|shiftin[7], shift:u4|shiftin[8], shift:u4|shiftin[0] ;
; C ; LC33 ; clk, state_graph:u5|state[1], state_graph:u5|state[0], state_graph:u5|srg4:u1|srg_4[1], state_graph:u5|state[2] ; state_graph:u5|input, state_graph:u5|state[1], state_graph:u5|state[2], state_graph:u5|state[0], state_graph:u5|load, state_graph:u5|isover, state_graph:u5|overflow ;
; C ; LC36 ; clk, state_graph:u5|state[1], state_graph:u5|state[0], state_graph:u5|state[2], state_graph:u5|isover, state_graph:u5|srg4:u1|srg_4[1] ; state_graph:u5|isover, quotient[0]~en ;
; C ; LC43 ; clk, state_graph:u5|isover ; quotient[1], quotient[2], quotient[3], remainder[0], remainder[1], remainder[2], remainder[3], quotient[0] ;
; C ; LC35 ; clk, shift:u4|shiftin[1] ; quotient[1] ;
+-----+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+---------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+----------------+
; Option ; Setting ;
+----------------------------------------------+----------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Security bit ; Off ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+----------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
Info: Processing started: Fri Jun 27 09:26:45 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off dividend4 -c dividend4
Info: Selected device EPM7128SLC84-6 for design "dividend4"
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Allocated 141 megabytes of memory during processing
Info: Processing ended: Fri Jun 27 09:26:46 2008
Info: Elapsed time: 00:00:01
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