dividend4.sim.rpt

本设计是一个八位被除数除以四位除数

; |dividend4|shift:u4|shiftin[2]             ; |dividend4|shift:u4|shiftin[2]             ; dataout          ;
; |dividend4|quotient[2]~reg0                ; |dividend4|quotient[2]~reg0                ; dataout          ;
; |dividend4|shift:u4|shiftin[3]             ; |dividend4|shift:u4|shiftin[3]             ; dataout          ;
; |dividend4|quotient[3]~reg0                ; |dividend4|quotient[3]~reg0                ; dataout          ;
; |dividend4|shift:u4|shiftin[4]             ; |dividend4|shift:u4|shiftin[4]             ; dataout          ;
; |dividend4|sub_5:u3|differin[0]            ; |dividend4|sub_5:u3|differin[0]            ; dataout          ;
; |dividend4|remainder[0]~reg0               ; |dividend4|remainder[0]~reg0               ; dataout          ;
; |dividend4|shift:u4|shiftin[5]             ; |dividend4|shift:u4|shiftin[5]             ; dataout          ;
; |dividend4|sub_5:u3|differin[1]            ; |dividend4|sub_5:u3|differin[1]            ; dataout          ;
; |dividend4|remainder[1]~reg0               ; |dividend4|remainder[1]~reg0               ; dataout          ;
; |dividend4|shift:u4|shiftin[6]             ; |dividend4|shift:u4|shiftin[6]             ; dataout          ;
; |dividend4|sub_5:u3|differin[2]            ; |dividend4|sub_5:u3|differin[2]            ; dataout          ;
; |dividend4|remainder[2]~reg0               ; |dividend4|remainder[2]~reg0               ; dataout          ;
; |dividend4|shift:u4|shiftin[7]             ; |dividend4|shift:u4|shiftin[7]             ; dataout          ;
; |dividend4|sub_5:u3|differin~55            ; |dividend4|sub_5:u3|differin~55            ; dataout          ;
; |dividend4|sub_5:u3|differin~56            ; |dividend4|sub_5:u3|differin~56            ; dataout          ;
; |dividend4|sub_5:u3|differin~58            ; |dividend4|sub_5:u3|differin~58            ; dataout          ;
; |dividend4|sub_5:u3|differin[3]            ; |dividend4|sub_5:u3|differin[3]            ; dataout          ;
; |dividend4|remainder[3]~reg0               ; |dividend4|remainder[3]~reg0               ; dataout          ;
; |dividend4|shift:u4|shiftin[8]             ; |dividend4|shift:u4|shiftin[8]             ; dataout          ;
; |dividend4|diag_c:u2|c                     ; |dividend4|diag_c:u2|c                     ; dataout          ;
; |dividend4|shift:u4|shiftin[0]             ; |dividend4|shift:u4|shiftin[0]             ; dataout          ;
; |dividend4|quotient[0]~reg0                ; |dividend4|quotient[0]~reg0                ; dataout          ;
; |dividend4|sub_5:u3|differin~67            ; |dividend4|sub_5:u3|differin~67            ; pexpout          ;
; |dividend4|sub_5:u3|differin~69            ; |dividend4|sub_5:u3|differin~69            ; pexpout          ;
; |dividend4|sub_5:u3|differin~75            ; |dividend4|sub_5:u3|differin~75            ; pexpout          ;
; |dividend4|sub_5:u3|differin~80            ; |dividend4|sub_5:u3|differin~80            ; pexpout          ;
; |dividend4|clk                             ; |dividend4|clk~corein                      ; dataout          ;
; |dividend4|st                              ; |dividend4|st~corein                       ; dataout          ;
+--------------------------------------------+--------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                   ;
+------------------------------------+------------------------------------+------------------+
; Node Name                          ; Output Port Name                   ; Output Port Type ;
+------------------------------------+------------------------------------+------------------+
; |dividend4|sub_5:u3|differin~54    ; |dividend4|sub_5:u3|differin~54    ; dataout          ;
; |dividend4|sub_5:u3|differin~57    ; |dividend4|sub_5:u3|differin~57    ; dataout          ;
; |dividend4|diag_c:u2|LessThan0~369 ; |dividend4|diag_c:u2|LessThan0~369 ; dataout          ;
; |dividend4|dividend_in[0]          ; |dividend4|dividend_in[0]~corein   ; dataout          ;
; |dividend4|dividend_in[1]          ; |dividend4|dividend_in[1]~corein   ; dataout          ;
; |dividend4|dividend_in[2]          ; |dividend4|dividend_in[2]~corein   ; dataout          ;
; |dividend4|dividend_in[3]          ; |dividend4|dividend_in[3]~corein   ; dataout          ;
; |dividend4|dividend_in[4]          ; |dividend4|dividend_in[4]~corein   ; dataout          ;
; |dividend4|dividend_in[5]          ; |dividend4|dividend_in[5]~corein   ; dataout          ;
; |dividend4|dividend_in[6]          ; |dividend4|dividend_in[6]~corein   ; dataout          ;
; |dividend4|dividend_in[7]          ; |dividend4|dividend_in[7]~corein   ; dataout          ;
; |dividend4|divisor[0]              ; |dividend4|divisor[0]~corein       ; dataout          ;
; |dividend4|divisor[1]              ; |dividend4|divisor[1]~corein       ; dataout          ;
; |dividend4|divisor[2]              ; |dividend4|divisor[2]~corein       ; dataout          ;
; |dividend4|divisor[3]              ; |dividend4|divisor[3]~corein       ; dataout          ;
; |dividend4|quotient[2]             ; |dividend4|quotient[2]             ; padio            ;
; |dividend4|remainder[1]            ; |dividend4|remainder[1]            ; padio            ;
; |dividend4|remainder[3]            ; |dividend4|remainder[3]            ; padio            ;
; |dividend4|quotient[0]             ; |dividend4|quotient[0]             ; padio            ;
; |dividend4|overflow                ; |dividend4|overflow                ; padio            ;
+------------------------------------+------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                   ;
+------------------------------------+------------------------------------+------------------+
; Node Name                          ; Output Port Name                   ; Output Port Type ;
+------------------------------------+------------------------------------+------------------+
; |dividend4|quotient[0]~en          ; |dividend4|quotient[0]~en          ; dataout          ;
; |dividend4|sub_5:u3|differin~54    ; |dividend4|sub_5:u3|differin~54    ; dataout          ;
; |dividend4|sub_5:u3|differin~57    ; |dividend4|sub_5:u3|differin~57    ; dataout          ;
; |dividend4|diag_c:u2|LessThan0~369 ; |dividend4|diag_c:u2|LessThan0~369 ; dataout          ;
; |dividend4|dividend_in[0]          ; |dividend4|dividend_in[0]~corein   ; dataout          ;
; |dividend4|dividend_in[1]          ; |dividend4|dividend_in[1]~corein   ; dataout          ;
; |dividend4|dividend_in[2]          ; |dividend4|dividend_in[2]~corein   ; dataout          ;
; |dividend4|dividend_in[3]          ; |dividend4|dividend_in[3]~corein   ; dataout          ;
; |dividend4|dividend_in[4]          ; |dividend4|dividend_in[4]~corein   ; dataout          ;
; |dividend4|dividend_in[5]          ; |dividend4|dividend_in[5]~corein   ; dataout          ;
; |dividend4|dividend_in[6]          ; |dividend4|dividend_in[6]~corein   ; dataout          ;
; |dividend4|dividend_in[7]          ; |dividend4|dividend_in[7]~corein   ; dataout          ;
; |dividend4|divisor[0]              ; |dividend4|divisor[0]~corein       ; dataout          ;
; |dividend4|divisor[1]              ; |dividend4|divisor[1]~corein       ; dataout          ;
; |dividend4|divisor[2]              ; |dividend4|divisor[2]~corein       ; dataout          ;
; |dividend4|divisor[3]              ; |dividend4|divisor[3]~corein       ; dataout          ;
; |dividend4|quotient[1]             ; |dividend4|quotient[1]             ; padio            ;
; |dividend4|quotient[3]             ; |dividend4|quotient[3]             ; padio            ;
; |dividend4|remainder[0]            ; |dividend4|remainder[0]            ; padio            ;
; |dividend4|remainder[2]            ; |dividend4|remainder[2]            ; padio            ;
; |dividend4|overflow                ; |dividend4|overflow                ; padio            ;
+------------------------------------+------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sun May 11 09:14:22 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off dividend4 -c dividend4
Info: Using vector source file "D:/altera/myproject/dividend4/dividend4.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      59.68 %
Info: Number of transitions in simulation is 364
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 98 megabytes of memory during processing
    Info: Processing ended: Sun May 11 09:14:23 2008
    Info: Elapsed time: 00:00:01