dividend4.map.rpt

本设计是一个八位被除数除以四位除数

; Total Number of Removed Registers = 8 ;                            ;
+---------------------------------------+----------------------------+


+----------------------------------------------------------------+
; Source assignments for sub_5:u3|lpm_add_sub:Add0|addcore:adder ;
+---------------------------+-------+------+---------------------+
; Assignment                ; Value ; From ; To                  ;
+---------------------------+-------+------+---------------------+
; SUPPRESS_DA_RULE_INTERNAL ; A103  ; -    ; -                   ;
+---------------------------+-------+------+---------------------+


+---------------------------------------------------------------------------------+
; Source assignments for sub_5:u3|lpm_add_sub:Add0|addcore:adder|addcore:adder[0] ;
+---------------------------+-------+------+--------------------------------------+
; Assignment                ; Value ; From ; To                                   ;
+---------------------------+-------+------+--------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; A103  ; -    ; -                                    ;
+---------------------------+-------+------+--------------------------------------+


+----------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sub_5:u3|lpm_add_sub:Add0 ;
+------------------------+-------------+-------------------------------------+
; Parameter Name         ; Value       ; Type                                ;
+------------------------+-------------+-------------------------------------+
; LPM_WIDTH              ; 5           ; Untyped                             ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                             ;
; LPM_DIRECTION          ; ADD         ; Untyped                             ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                             ;
; LPM_PIPELINE           ; 0           ; Untyped                             ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                             ;
; REGISTERED_AT_END      ; 0           ; Untyped                             ;
; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                             ;
; USE_CS_BUFFERS         ; 1           ; Untyped                             ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                             ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                  ;
; DEVICE_FAMILY          ; MAX7000S    ; Untyped                             ;
; USE_WYS                ; OFF         ; Untyped                             ;
; STYLE                  ; FAST        ; Untyped                             ;
; CBXI_PARAMETER         ; add_sub_a9h ; Untyped                             ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                          ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                        ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                        ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                      ;
+------------------------+-------------+-------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Fri Jun 27 09:26:41 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dividend4 -c dividend4
Info: Found 2 design units, including 1 entities, in source file dividend4.vhd
    Info: Found design unit 1: dividend4-behavioral
    Info: Found entity 1: dividend4
Info: Found 2 design units, including 1 entities, in source file load_n.vhd
    Info: Found design unit 1: load_n-behav
    Info: Found entity 1: load_n
Info: Found 2 design units, including 1 entities, in source file sub_5.vhd
    Info: Found design unit 1: sub_5-behav
    Info: Found entity 1: sub_5
Info: Found 2 design units, including 1 entities, in source file state_graph.vhd
    Info: Found design unit 1: state_graph-behavioral
    Info: Found entity 1: state_graph
Info: Found 2 design units, including 1 entities, in source file srg4.vhd
    Info: Found design unit 1: srg4-behav
    Info: Found entity 1: srg4
Info: Found 2 design units, including 1 entities, in source file shift.vhd
    Info: Found design unit 1: shift-behav
    Info: Found entity 1: shift
Info: Found 2 design units, including 1 entities, in source file diag_c.vhd
    Info: Found design unit 1: diag_c-behav
    Info: Found entity 1: diag_c
Info: Found 2 design units, including 1 entities, in source file get_res.vhd
    Info: Found design unit 1: get_res-behav
    Info: Found entity 1: get_res
Info: Elaborating entity "dividend4" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at dividend4.vhd(70): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "load_n" for hierarchy "load_n:u1"
Info: Elaborating entity "diag_c" for hierarchy "diag_c:u2"
Info: Elaborating entity "sub_5" for hierarchy "sub_5:u3"
Info: Elaborating entity "shift" for hierarchy "shift:u4"
Warning (10492): VHDL Process Statement warning at shift.vhd(16): signal "load" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "state_graph" for hierarchy "state_graph:u5"
Info: Elaborating entity "srg4" for hierarchy "state_graph:u5|srg4:u1"
Info: Inferred 1 megafunctions from design logic
    Info: Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "sub_5:u3|Add0"
Info: Found 1 design units, including 1 entities, in source file ../../72/quartus/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Elaborated megafunction instantiation "sub_5:u3|lpm_add_sub:Add0"
Info: Found 1 design units, including 1 entities, in source file ../../72/quartus/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Elaborated megafunction instantiation "sub_5:u3|lpm_add_sub:Add0|addcore:adder", which is child of megafunction instantiation "sub_5:u3|lpm_add_sub:Add0"
Info: Instantiated megafunction "sub_5:u3|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "5"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Found 1 design units, including 1 entities, in source file ../../72/quartus/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Elaborated megafunction instantiation "sub_5:u3|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "sub_5:u3|lpm_add_sub:Add0"
Info: Instantiated megafunction "sub_5:u3|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "5"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Elaborated megafunction instantiation "sub_5:u3|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "sub_5:u3|lpm_add_sub:Add0"
Info: Instantiated megafunction "sub_5:u3|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "5"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Elaborated megafunction instantiation "sub_5:u3|lpm_add_sub:Add0|addcore:adder|addcore:adder[0]", which is child of megafunction instantiation "sub_5:u3|lpm_add_sub:Add0"
Info: Instantiated megafunction "sub_5:u3|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "5"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Elaborated megafunction instantiation "sub_5:u3|lpm_add_sub:Add0|addcore:adder|addcore:adder[0]|a_csnbuffer:oflow_node", which is child of megafunction instantiation "sub_5:u3|lpm_add_sub:Add0"
Info: Instantiated megafunction "sub_5:u3|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "5"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Elaborated megafunction instantiation "sub_5:u3|lpm_add_sub:Add0|addcore:adder|addcore:adder[0]|a_csnbuffer:result_node", which is child of megafunction instantiation "sub_5:u3|lpm_add_sub:Add0"
Info: Instantiated megafunction "sub_5:u3|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "5"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Found 1 design units, including 1 entities, in source file ../../72/quartus/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Elaborated megafunction instantiation "sub_5:u3|lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "sub_5:u3|lpm_add_sub:Add0"
Info: Instantiated megafunction "sub_5:u3|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "5"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Elaborated megafunction instantiation "sub_5:u3|lpm_add_sub:Add0|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "sub_5:u3|lpm_add_sub:Add0"
Info: Instantiated megafunction "sub_5:u3|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "5"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Duplicate registers merged to single register
    Info: Duplicate register "remainder[3]~en" merged to single register "quotient[0]~en"
    Info: Duplicate register "remainder[2]~en" merged to single register "quotient[0]~en"
    Info: Duplicate register "remainder[1]~en" merged to single register "quotient[0]~en"
    Info: Duplicate register "remainder[0]~en" merged to single register "quotient[0]~en"
    Info: Duplicate register "quotient[3]~en" merged to single register "quotient[0]~en"
    Info: Duplicate register "quotient[2]~en" merged to single register "quotient[0]~en"
    Info: Duplicate register "quotient[1]~en" merged to single register "quotient[0]~en"
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below.
    Info: Register "sub_5:u3|differin[4]" lost all its fanouts during netlist optimizations.
Info: Implemented 66 device resources after synthesis - the final resource count might be different
    Info: Implemented 14 input pins
    Info: Implemented 9 output pins
    Info: Implemented 37 macrocells
    Info: Implemented 6 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Allocated 159 megabytes of memory during processing
    Info: Processing ended: Fri Jun 27 09:26:44 2008
    Info: Elapsed time: 00:00:03