prev_cmp_dividend4.tan.qmsg

本设计是一个八位被除数除以四位除数

{ "Info" "ITDB_FULL_TCO_RESULT" "clk quotient\[0\] quotient\[0\]~en 9.700 ns register " "Info: tco from clock \"clk\" to destination pin \"quotient\[0\]\" through register \"quotient\[0\]~en\" is 9.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.200 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 19 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dividend4.vhd" "" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns quotient\[0\]~en 2 REG LC16 8 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC16; Fanout = 8; REG Node = 'quotient\[0\]~en'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { clk quotient[0]~en } "NODE_NAME" } } { "dividend4.vhd" "" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 70 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 100.00 % ) " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { clk quotient[0]~en } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { clk {} clk~out {} quotient[0]~en {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" {  } { { "dividend4.vhd" "" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 70 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.100 ns + Longest register pin " "Info: + Longest register to pin delay is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns quotient\[0\]~en 1 REG LC16 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC16; Fanout = 8; REG Node = 'quotient\[0\]~en'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { quotient[0]~en } "NODE_NAME" } } { "dividend4.vhd" "" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 70 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(4.700 ns) 6.100 ns quotient\[0\] 2 PIN PIN_21 0 " "Info: 2: + IC(1.400 ns) + CELL(4.700 ns) = 6.100 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'quotient\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { quotient[0]~en quotient[0] } "NODE_NAME" } } { "dividend4.vhd" "" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 70 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.700 ns ( 77.05 % ) " "Info: Total cell delay = 4.700 ns ( 77.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 22.95 % ) " "Info: Total interconnect delay = 1.400 ns ( 22.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { quotient[0]~en quotient[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.100 ns" { quotient[0]~en {} quotient[0] {} } { 0.000ns 1.400ns } { 0.000ns 4.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { clk quotient[0]~en } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { clk {} clk~out {} quotient[0]~en {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { quotient[0]~en quotient[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.100 ns" { quotient[0]~en {} quotient[0] {} } { 0.000ns 1.400ns } { 0.000ns 4.700ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "sub_5:u3\|differin\[3\] divisor\[3\] clk 5.300 ns register " "Info: th for register \"sub_5:u3\|differin\[3\]\" (data pin = \"divisor\[3\]\", clock pin = \"clk\") is 5.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.200 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 19 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 19; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dividend4.vhd" "" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.600 ns state_graph:u5\|srg4:u1\|srg_4\[1\] 2 REG LC10 16 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.600 ns; Loc. = LC10; Fanout = 16; REG Node = 'state_graph:u5\|srg4:u1\|srg_4\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { clk state_graph:u5|srg4:u1|srg_4[1] } "NODE_NAME" } } { "srg4.vhd" "" { Text "D:/altera/myproject/dividend4/srg4.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(3.100 ns) 8.200 ns sub_5:u3\|differin\[3\] 3 REG LC8 2 " "Info: 3: + IC(1.500 ns) + CELL(3.100 ns) = 8.200 ns; Loc. = LC8; Fanout = 2; REG Node = 'sub_5:u3\|differin\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { state_graph:u5|srg4:u1|srg_4[1] sub_5:u3|differin[3] } "NODE_NAME" } } { "sub_5.vhd" "" { Text "D:/altera/myproject/dividend4/sub_5.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.700 ns ( 81.71 % ) " "Info: Total cell delay = 6.700 ns ( 81.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns ( 18.29 % ) " "Info: Total interconnect delay = 1.500 ns ( 18.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.200 ns" { clk state_graph:u5|srg4:u1|srg_4[1] sub_5:u3|differin[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.200 ns" { clk {} clk~out {} state_graph:u5|srg4:u1|srg_4[1] {} sub_5:u3|differin[3] {} } { 0.000ns 0.000ns 0.000ns 1.500ns } { 0.000ns 1.600ns 2.000ns 3.100ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" {  } { { "sub_5.vhd" "" { Text "D:/altera/myproject/dividend4/sub_5.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.600 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns divisor\[3\] 1 PIN PIN_51 13 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_51; Fanout = 13; PIN Node = 'divisor\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { divisor[3] } "NODE_NAME" } } { "dividend4.vhd" "" { Text "D:/altera/myproject/dividend4/dividend4.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(3.000 ns) 4.600 ns sub_5:u3\|differin\[3\] 2 REG LC8 2 " "Info: 2: + IC(1.400 ns) + CELL(3.000 ns) = 4.600 ns; Loc. = LC8; Fanout = 2; REG Node = 'sub_5:u3\|differin\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { divisor[3] sub_5:u3|differin[3] } "NODE_NAME" } } { "sub_5.vhd" "" { Text "D:/altera/myproject/dividend4/sub_5.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 69.57 % ) " "Info: Total cell delay = 3.200 ns ( 69.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 30.43 % ) " "Info: Total interconnect delay = 1.400 ns ( 30.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { divisor[3] sub_5:u3|differin[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.600 ns" { divisor[3] {} divisor[3]~out {} sub_5:u3|differin[3] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 3.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.200 ns" { clk state_graph:u5|srg4:u1|srg_4[1] sub_5:u3|differin[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.200 ns" { clk {} clk~out {} state_graph:u5|srg4:u1|srg_4[1] {} sub_5:u3|differin[3] {} } { 0.000ns 0.000ns 0.000ns 1.500ns } { 0.000ns 1.600ns 2.000ns 3.100ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { divisor[3] sub_5:u3|differin[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.600 ns" { divisor[3] {} divisor[3]~out {} sub_5:u3|differin[3] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 3.000ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "109 " "Info: Allocated 109 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 11 08:49:29 2008 " "Info: Processing ended: Sun May 11 08:49:29 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}