diag_c.vhd

本设计是一个八位被除数除以四位除数

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity diag_c is
	port(comp1:in std_logic_vector(4 downto 0);
		comp2:in std_logic_vector(4 downto 0);
		diag:in std_logic;
		c:out std_logic);
	end diag_c;
architecture behav of diag_c is
begin
   process(comp1,comp2,diag)
	begin
	if diag'event and diag='1' then
	if comp1>=comp2 then c<='1';else c<='0';end if;
	end if;
	end process;
end behav;