get_res.vhd

来自「本设计是一个八位被除数除以四位除数」· VHDL 代码 · 共 16 行

library ieee;
use ieee.std_logic_1164.all;
entity get_res is
port(isover:in std_logic;
complete:out std_logic
);
end get_res;
architecture behav of get_res is
begin
	u1:process(isover)
	begin
	if isover'event and isover='1' then
		complete<='1';
	end if;
	end process u1;
end behav;