📄 altfp_div0.vhd
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loop32 : FOR j IN 0 TO 26 GENERATE
wire_mux46_data_2d(i, j) <= qkd_mux_input_w(i*27+j);
END GENERATE loop32;
END GENERATE loop31;
mux46 : lpm_mux
GENERIC MAP (
LPM_SIZE => 4,
LPM_WIDTH => 27,
LPM_WIDTHS => 2
)
PORT MAP (
data => wire_mux46_data_2d,
result => wire_mux46_result,
sel => rom_mux_w(1 DOWNTO 0)
);
qds_block45 : altfp_div0_qds_block_7o8
PORT MAP (
aclr => aclr,
clken => clken,
clock => clock,
decoder_bus => rom_add_w,
decoder_output => wire_qds_block45_decoder_output
);
END RTL; --altfp_div0_srt_block_int_q4k
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_add_sub 51 lpm_compare 56 lpm_mux 28 lut 1908
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altfp_div0_altfp_div_srt_ext_sbd IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
denom : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
divider : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
numer : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
quotient : OUT STD_LOGIC_VECTOR (27 DOWNTO 0);
remain : OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
);
END altfp_div0_altfp_div_srt_ext_sbd;
ARCHITECTURE RTL OF altfp_div0_altfp_div_srt_ext_sbd IS
ATTRIBUTE synthesis_clearbox : boolean;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL divider_next_special_dffe : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL Rk_remainder_special_dffe : STD_LOGIC_VECTOR(26 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL rom_reg_dffe0c : STD_LOGIC_VECTOR(49 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_rom_reg_dffe0c_w785w : STD_LOGIC_VECTOR (49 DOWNTO 0);
SIGNAL rom_reg_dffe10c : STD_LOGIC_VECTOR(14 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_rom_reg_dffe10c_w805w : STD_LOGIC_VECTOR (14 DOWNTO 0);
SIGNAL rom_reg_dffe11c : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_rom_reg_dffe11c_w807w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL rom_reg_dffe12c : STD_LOGIC_VECTOR(2 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_rom_reg_dffe12c_w809w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_reg_dffe1c : STD_LOGIC_VECTOR(68 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_rom_reg_dffe1c_w787w : STD_LOGIC_VECTOR (68 DOWNTO 0);
SIGNAL rom_reg_dffe2c : STD_LOGIC_VECTOR(62 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_rom_reg_dffe2c_w789w : STD_LOGIC_VECTOR (62 DOWNTO 0);
SIGNAL rom_reg_dffe3c : STD_LOGIC_VECTOR(56 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_rom_reg_dffe3c_w791w : STD_LOGIC_VECTOR (56 DOWNTO 0);
SIGNAL rom_reg_dffe4c : STD_LOGIC_VECTOR(50 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_rom_reg_dffe4c_w793w : STD_LOGIC_VECTOR (50 DOWNTO 0);
SIGNAL rom_reg_dffe5c : STD_LOGIC_VECTOR(44 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_rom_reg_dffe5c_w795w : STD_LOGIC_VECTOR (44 DOWNTO 0);
SIGNAL rom_reg_dffe6c : STD_LOGIC_VECTOR(38 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_rom_reg_dffe6c_w797w : STD_LOGIC_VECTOR (38 DOWNTO 0);
SIGNAL rom_reg_dffe7c : STD_LOGIC_VECTOR(32 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_rom_reg_dffe7c_w799w : STD_LOGIC_VECTOR (32 DOWNTO 0);
SIGNAL rom_reg_dffe8c : STD_LOGIC_VECTOR(26 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_rom_reg_dffe8c_w801w : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL rom_reg_dffe9c : STD_LOGIC_VECTOR(20 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_rom_reg_dffe9c_w803w : STD_LOGIC_VECTOR (20 DOWNTO 0);
SIGNAL wire_add_sub21_w_lg_w_lg_cout1464w1465w : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL wire_add_sub21_w_lg_cout1463w : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL wire_add_sub21_w_lg_cout1464w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub21_w_lg_w_lg_w_lg_cout1464w1465w1466w : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL wire_add_sub21_cout : STD_LOGIC;
SIGNAL wire_add_sub21_result : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_add_sub22_result : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL wire_vcc : STD_LOGIC;
SIGNAL wire_add_sub23_result : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL wire_add_sub24_w_lg_w_lg_cout1480w1481w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_add_sub24_w_lg_cout1479w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_add_sub24_w_lg_cout1480w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub24_w_lg_w_lg_w_lg_cout1480w1481w1482w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_add_sub24_cout : STD_LOGIC;
SIGNAL wire_add_sub24_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_add_sub25_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_add_sub26_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_add_sub27_w_lg_w_lg_cout1487w1488w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_add_sub27_w_lg_cout1486w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_add_sub27_w_lg_cout1487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_add_sub27_w_lg_w_lg_w_lg_cout1487w1488w1489w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_add_sub27_cout : STD_LOGIC;
SIGNAL wire_add_sub27_datab : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_add_sub27_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_add_sub28_datab : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_add_sub28_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_add_sub29_datab : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_add_sub29_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_srt_block_int10_divider_reg : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_srt_block_int10_Rk_next : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_srt_block_int10_rom : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_srt_block_int11_divider_reg : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_srt_block_int11_Rk_next : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_srt_block_int11_rom : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_srt_block_int12_divider_reg : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_srt_block_int12_Rk_next : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_srt_block_int12_rom : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_srt_block_int13_divider_reg : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_srt_block_int13_Rk_next : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_srt_block_int13_rom : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_srt_block_int14_divider_reg : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_srt_block_int14_Rk_next : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_srt_block_int14_rom : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_srt_block_int15_divider_reg : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_srt_block_int15_Rk_next : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_srt_block_int15_rom : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_srt_block_int16_divider_reg : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_srt_block_int16_Rk_next : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_srt_block_int16_rom : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_srt_block_int17_divider_reg : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_srt_block_int17_Rk_next : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_srt_block_int17_rom : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_srt_block_int18_divider_reg : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_srt_block_int18_Rk_next : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_srt_block_int18_rom : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_srt_block_int19_divider_reg : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_srt_block_int19_Rk_next : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_srt_block_int19_rom : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_srt_block_int20_divider_reg : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_srt_block_int20_Rk_next : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL wire_srt_block_int20_rom : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_srt_block_int7_divider_reg : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_srt_block_int7_Rk_next : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_srt_block_int7_rom : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_srt_block_int8_divider_reg : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_srt_block_int8_Rk_next : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_srt_block_int8_rom : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_srt_block_int9_divider_reg : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_srt_block_int9_Rk_next : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_srt_block_int9_rom : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_mux_remainder_w1470w1492w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_mux_remainder_w1470w1471w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1283w1311w1381w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1283w1311w1312w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1303w1361w1411w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1303w1361w1362w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1305w1366w1414w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1305w1366w1367w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1307w1371w1417w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1307w1371w1372w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1309w1376w1420w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1309w1376w1377w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1285w1316w1384w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1285w1316w1317w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1287w1321w1387w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1287w1321w1322w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1289w1326w1390w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1289w1326w1327w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1291w1331w1393w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1291w1331w1332w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1293w1336w1396w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1293w1336w1337w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1295w1341w1399w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1295w1341w1342w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1297w1346w1402w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1297w1346w1347w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1299w1351w1405w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1299w1351w1352w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1301w1356w1408w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_lg_w_rom_mux_w_range1301w1356w1357w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_mux_remainder_w1468w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_mux_remainder_w1491w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1283w1313w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1283w1380w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1303w1363w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1303w1410w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1305w1368w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1305w1413w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1307w1373w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1307w1416w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1309w1378w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1309w1419w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1285w1318w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1285w1383w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1287w1323w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1287w1386w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1289w1328w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1289w1389w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1291w1333w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1291w1392w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1293w1338w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1293w1395w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1295w1343w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1295w1398w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1297w1348w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1297w1401w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1299w1353w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1299w1404w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1301w1358w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1301w1407w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_mux_remainder_w1470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1283w1311w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1303w1361w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1305w1366w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1307w1371w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1309w1376w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1285w1316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1287w1321w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1289w1326w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1291w1331w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1293w1336w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1295w1341w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1297w1346w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_rom_mux_w_range1299w1351w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_srt_ext1_w_lg_w_r⌨️ 快捷键说明
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