altfp_div0.vhd

本设计是一个八位被除数除以四位除数

		LPM_WIDTH => 9
	  )
	  PORT MAP ( 
		aleb => wire_cmpr52_aleb,
		dataa => Rk_w,
		datab => mk_pos0_w
	  );
	cmpr53 :  lpm_compare
	  GENERIC MAP (
		LPM_REPRESENTATION => "SIGNED",
		LPM_WIDTH => 9
	  )
	  PORT MAP ( 
		aleb => wire_cmpr53_aleb,
		dataa => Rk_w,
		datab => mk_pos1_w
	  );
	cmpr54 :  lpm_compare
	  GENERIC MAP (
		LPM_REPRESENTATION => "SIGNED",
		LPM_WIDTH => 9
	  )
	  PORT MAP ( 
		aleb => wire_cmpr54_aleb,
		dataa => Rk_w,
		datab => mk_pos2_w
	  );
	loop26 : FOR i IN 0 TO 15 GENERATE
		loop27 : FOR j IN 0 TO 31 GENERATE
			wire_mux50_data_2d(i, j) <= mk_bus_const_w(i*32+j);
		END GENERATE loop27;
	END GENERATE loop26;
	mux50 :  lpm_mux
	  GENERIC MAP (
		LPM_SIZE => 16,
		LPM_WIDTH => 32,
		LPM_WIDTHS => 4
	  )
	  PORT MAP ( 
		data => wire_mux50_data_2d,
		result => wire_mux50_result,
		sel => Div_w
	  );

 END RTL; --altfp_div0_qds_block_7o8

 LIBRARY lpm;
 USE lpm.lpm_components.all;

--synthesis_resources = lpm_add_sub 3 lpm_compare 4 lpm_mux 2 lut 100 
 LIBRARY ieee;
 USE ieee.std_logic_1164.all;

 ENTITY  altfp_div0_srt_block_int_q4k IS 
	 PORT 
	 ( 
		 aclr	:	IN  STD_LOGIC := '0';
		 clken	:	IN  STD_LOGIC := '1';
		 clock	:	IN  STD_LOGIC := '0';
		 divider	:	IN  STD_LOGIC_VECTOR (23 DOWNTO 0);
		 divider_reg	:	OUT  STD_LOGIC_VECTOR (23 DOWNTO 0);
		 Rk	:	IN  STD_LOGIC_VECTOR (23 DOWNTO 0);
		 Rk_next	:	OUT  STD_LOGIC_VECTOR (24 DOWNTO 0);
		 rom	:	OUT  STD_LOGIC_VECTOR (2 DOWNTO 0)
	 ); 
 END altfp_div0_srt_block_int_q4k;

 ARCHITECTURE RTL OF altfp_div0_srt_block_int_q4k IS

	 ATTRIBUTE synthesis_clearbox : boolean;
	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
	 SIGNAL	 divider_dffe	:	STD_LOGIC_VECTOR(22 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	 divider_dffe_1a	:	STD_LOGIC_VECTOR(22 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	 Rk_dffe	:	STD_LOGIC_VECTOR(23 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	 Rk_next_dffe	:	STD_LOGIC_VECTOR(24 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	 rom_out_dffe	:	STD_LOGIC_VECTOR(2 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL  wire_add_sub47_w_lg_w_lg_cout1701w1702w	:	STD_LOGIC_VECTOR (10 DOWNTO 0);
	 SIGNAL  wire_add_sub47_w_lg_cout1699w	:	STD_LOGIC_VECTOR (10 DOWNTO 0);
	 SIGNAL  wire_add_sub47_w_lg_cout1701w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_add_sub47_w_lg_w_lg_w_lg_cout1701w1702w1703w	:	STD_LOGIC_VECTOR (10 DOWNTO 0);
	 SIGNAL  wire_add_sub47_cout	:	STD_LOGIC;
	 SIGNAL  wire_add_sub47_result	:	STD_LOGIC_VECTOR (13 DOWNTO 0);
	 SIGNAL  wire_gnd	:	STD_LOGIC;
	 SIGNAL  wire_add_sub48_result	:	STD_LOGIC_VECTOR (12 DOWNTO 0);
	 SIGNAL  wire_add_sub48_w_result_range1700w	:	STD_LOGIC_VECTOR (10 DOWNTO 0);
	 SIGNAL  wire_vcc	:	STD_LOGIC;
	 SIGNAL  wire_add_sub49_result	:	STD_LOGIC_VECTOR (12 DOWNTO 0);
	 SIGNAL  wire_add_sub49_w_result_range1698w	:	STD_LOGIC_VECTOR (10 DOWNTO 0);
	 SIGNAL  wire_mux46_data_2d	:	STD_LOGIC_2D(3 DOWNTO 0, 26 DOWNTO 0);
	 SIGNAL  wire_mux46_result	:	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  wire_qds_block45_decoder_output	:	STD_LOGIC_VECTOR (2 DOWNTO 0);
	 SIGNAL  divider_1D_w :	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  divider_2D_w :	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  divider_dffe_1a_w :	STD_LOGIC_VECTOR (22 DOWNTO 0);
	 SIGNAL  divider_dffe_w :	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  divider_in_w :	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  padded_2_zeros_w :	STD_LOGIC_VECTOR (1 DOWNTO 0);
	 SIGNAL  padded_3_zeros_w :	STD_LOGIC_VECTOR (2 DOWNTO 0);
	 SIGNAL  pos_qk0d_int_w :	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  pos_qk1d_int_w :	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  pos_qk2d_int_w :	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  qkd_mux_input_w :	STD_LOGIC_VECTOR (107 DOWNTO 0);
	 SIGNAL  qkd_mux_w :	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  Rk_adder_padded_w :	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  Rk_dffe_1a_w :	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  Rk_in_w :	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  Rk_next_dffe_w :	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  rom_add_w :	STD_LOGIC_VECTOR (11 DOWNTO 0);
	 SIGNAL  rom_mux_w :	STD_LOGIC_VECTOR (2 DOWNTO 0);
	 SIGNAL  rom_out_1a_w :	STD_LOGIC_VECTOR (2 DOWNTO 0);
	 SIGNAL  rom_out_dffe_w :	STD_LOGIC_VECTOR (2 DOWNTO 0);
	 SIGNAL  srt_adder_w :	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_srt_block_int7_w_divider_in_w_range1669w	:	STD_LOGIC_VECTOR (22 DOWNTO 0);
	 COMPONENT  lpm_add_sub
	 GENERIC 
	 (
		LPM_DIRECTION	:	STRING := "DEFAULT";
		LPM_PIPELINE	:	NATURAL := 0;
		LPM_REPRESENTATION	:	STRING := "SIGNED";
		LPM_WIDTH	:	NATURAL;
		lpm_hint	:	STRING := "UNUSED";
		lpm_type	:	STRING := "lpm_add_sub"
	 );
	 PORT
	 ( 
		aclr	:	IN STD_LOGIC := '0';
		add_sub	:	IN STD_LOGIC := '1';
		cin	:	IN STD_LOGIC := 'Z';
		clken	:	IN STD_LOGIC := '1';
		clock	:	IN STD_LOGIC := '0';
		cout	:	OUT STD_LOGIC;
		dataa	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
		datab	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
		overflow	:	OUT STD_LOGIC;
		result	:	OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
	 ); 
	 END COMPONENT;
	 COMPONENT  altfp_div0_qds_block_7o8
	 PORT
	 ( 
		aclr	:	IN  STD_LOGIC := '0';
		clken	:	IN  STD_LOGIC := '1';
		clock	:	IN  STD_LOGIC := '0';
		decoder_bus	:	IN  STD_LOGIC_VECTOR(11 DOWNTO 0);
		decoder_output	:	OUT  STD_LOGIC_VECTOR(2 DOWNTO 0)
	 ); 
	 END COMPONENT;
 BEGIN

	wire_gnd <= '0';
	wire_vcc <= '1';
	divider_1D_w <= ( padded_3_zeros_w & "1" & divider_dffe_1a_w);
	divider_2D_w <= ( padded_2_zeros_w & "1" & divider_dffe_1a_w & "0");
	divider_dffe_1a_w <= divider_dffe_1a;
	divider_dffe_w <= ( "1" & divider_dffe);
	divider_in_w <= divider;
	divider_reg <= divider_dffe_w;
	padded_2_zeros_w <= "00";
	padded_3_zeros_w <= "000";
	pos_qk0d_int_w <= "000000000000000000000000000";
	pos_qk1d_int_w <= divider_1D_w;
	pos_qk2d_int_w <= divider_2D_w;
	qkd_mux_input_w <= ( pos_qk2d_int_w & pos_qk2d_int_w & pos_qk1d_int_w & pos_qk0d_int_w);
	qkd_mux_w <= wire_mux46_result;
	Rk_adder_padded_w <= ( padded_3_zeros_w & Rk_dffe);
	Rk_dffe_1a_w <= Rk_in_w;
	Rk_in_w <= Rk;
	Rk_next <= Rk_next_dffe_w;
	Rk_next_dffe_w <= Rk_next_dffe;
	rom <= rom_out_dffe_w;
	rom_add_w <= ( padded_3_zeros_w & Rk_in_w(23 DOWNTO 19) & divider_in_w(22 DOWNTO 19));
	rom_mux_w <= rom_out_1a_w;
	rom_out_1a_w <= wire_qds_block45_decoder_output;
	rom_out_dffe_w <= rom_out_dffe;
	srt_adder_w <= ( wire_add_sub47_w_lg_w_lg_w_lg_cout1701w1702w1703w & wire_add_sub47_result);
	wire_srt_block_int7_w_divider_in_w_range1669w <= divider_in_w(22 DOWNTO 0);
	PROCESS (clock, aclr)
	BEGIN
		IF (aclr = '1') THEN divider_dffe <= (OTHERS => '0');
		ELSIF (clock = '1' AND clock'event) THEN 
			IF (clken = '1') THEN divider_dffe <= divider_dffe_1a_w;
			END IF;
		END IF;
	END PROCESS;
	PROCESS (clock, aclr)
	BEGIN
		IF (aclr = '1') THEN divider_dffe_1a <= (OTHERS => '0');
		ELSIF (clock = '1' AND clock'event) THEN 
			IF (clken = '1') THEN divider_dffe_1a <= divider_in_w(22 DOWNTO 0);
			END IF;
		END IF;
	END PROCESS;
	PROCESS (clock, aclr)
	BEGIN
		IF (aclr = '1') THEN Rk_dffe <= (OTHERS => '0');
		ELSIF (clock = '1' AND clock'event) THEN 
			IF (clken = '1') THEN Rk_dffe <= Rk_dffe_1a_w;
			END IF;
		END IF;
	END PROCESS;
	PROCESS (clock, aclr)
	BEGIN
		IF (aclr = '1') THEN Rk_next_dffe <= (OTHERS => '0');
		ELSIF (clock = '1' AND clock'event) THEN 
			IF (clken = '1') THEN Rk_next_dffe <= srt_adder_w;
			END IF;
		END IF;
	END PROCESS;
	PROCESS (clock, aclr)
	BEGIN
		IF (aclr = '1') THEN rom_out_dffe <= (OTHERS => '0');
		ELSIF (clock = '1' AND clock'event) THEN 
			IF (clken = '1') THEN rom_out_dffe <= rom_out_1a_w;
			END IF;
		END IF;
	END PROCESS;
	loop28 : FOR i IN 0 TO 10 GENERATE 
		wire_add_sub47_w_lg_w_lg_cout1701w1702w(i) <= wire_add_sub47_w_lg_cout1701w(0) AND wire_add_sub48_w_result_range1700w(i);
	END GENERATE loop28;
	loop29 : FOR i IN 0 TO 10 GENERATE 
		wire_add_sub47_w_lg_cout1699w(i) <= wire_add_sub47_cout AND wire_add_sub49_w_result_range1698w(i);
	END GENERATE loop29;
	wire_add_sub47_w_lg_cout1701w(0) <= NOT wire_add_sub47_cout;
	loop30 : FOR i IN 0 TO 10 GENERATE 
		wire_add_sub47_w_lg_w_lg_w_lg_cout1701w1702w1703w(i) <= wire_add_sub47_w_lg_w_lg_cout1701w1702w(i) OR wire_add_sub47_w_lg_cout1699w(i);
	END GENERATE loop30;
	add_sub47 :  lpm_add_sub
	  GENERIC MAP (
		LPM_WIDTH => 14,
		lpm_hint => "ONE_INPUT_IS_CONSTANT=NO"
	  )
	  PORT MAP ( 
		add_sub => rom_mux_w(2),
		cout => wire_add_sub47_cout,
		dataa => Rk_adder_padded_w(13 DOWNTO 0),
		datab => qkd_mux_w(13 DOWNTO 0),
		result => wire_add_sub47_result
	  );
	wire_add_sub48_w_result_range1700w <= wire_add_sub48_result(10 DOWNTO 0);
	add_sub48 :  lpm_add_sub
	  GENERIC MAP (
		LPM_WIDTH => 13,
		lpm_hint => "ONE_INPUT_IS_CONSTANT=NO"
	  )
	  PORT MAP ( 
		add_sub => rom_mux_w(2),
		cin => wire_gnd,
		dataa => Rk_adder_padded_w(26 DOWNTO 14),
		datab => qkd_mux_w(26 DOWNTO 14),
		result => wire_add_sub48_result
	  );
	wire_add_sub49_w_result_range1698w <= wire_add_sub49_result(10 DOWNTO 0);
	add_sub49 :  lpm_add_sub
	  GENERIC MAP (
		LPM_WIDTH => 13,
		lpm_hint => "ONE_INPUT_IS_CONSTANT=NO"
	  )
	  PORT MAP ( 
		add_sub => rom_mux_w(2),
		cin => wire_vcc,
		dataa => Rk_adder_padded_w(26 DOWNTO 14),
		datab => qkd_mux_w(26 DOWNTO 14),
		result => wire_add_sub49_result
	  );
	loop31 : FOR i IN 0 TO 3 GENERATE