📄 altfp_div0.vhd
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LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT altfp_div0_qds_block_6a7
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
decoder_bus : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
decoder_output : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
wire_gnd <= '0';
wire_vcc <= '1';
divider_1D_w <= ( padded_3_zeros_w & "1" & divider_dffe_1a_w);
divider_2D_w <= ( padded_2_zeros_w & "1" & divider_dffe_1a_w & "0");
divider_dffe_1a_w <= divider_dffe_1a;
divider_dffe_w <= ( "1" & divider_dffe_1a_w);
divider_in_w <= divider;
divider_reg <= divider_dffe_w;
padded_2_zeros_w <= "00";
padded_3_zeros_w <= "000";
pos_qk0d_int_w <= "000000000000000000000000000";
pos_qk1d_int_w <= divider_1D_w;
pos_qk2d_int_w <= divider_2D_w;
qkd_mux_input_w <= ( pos_qk2d_int_w & pos_qk2d_int_w & pos_qk1d_int_w & pos_qk0d_int_w);
qkd_mux_w <= wire_mux41_result;
Rk_adder_padded_w <= ( Rk_dffe & padded_2_zeros_w);
Rk_dffe_1a_w <= Rk_in_w;
Rk_in_w <= Rk;
Rk_next <= Rk_next_dffe_w;
Rk_next_dffe_w <= srt_adder_w;
rom <= rom_out_dffe_w;
rom_add_w <= ( Rk_in_w(24 DOWNTO 17) & divider_in_w(22 DOWNTO 19));
rom_mux_w <= rom_out_1a_w;
rom_out_1a_w <= wire_qds_block40_decoder_output;
rom_out_dffe_w <= rom_out_1a_w;
srt_adder_w <= ( wire_add_sub42_w_lg_w_lg_w_lg_cout1654w1655w1656w & wire_add_sub42_result);
wire_srt_block_int20_w_divider_in_w_range1622w <= divider_in_w(22 DOWNTO 0);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN divider_dffe_1a <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN divider_dffe_1a <= divider_in_w(22 DOWNTO 0);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN Rk_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN Rk_dffe <= Rk_dffe_1a_w;
END IF;
END IF;
END PROCESS;
loop14 : FOR i IN 0 TO 12 GENERATE
wire_add_sub42_w_lg_w_lg_cout1654w1655w(i) <= wire_add_sub42_w_lg_cout1654w(0) AND wire_add_sub43_w_result_range1653w(i);
END GENERATE loop14;
loop15 : FOR i IN 0 TO 12 GENERATE
wire_add_sub42_w_lg_cout1652w(i) <= wire_add_sub42_cout AND wire_add_sub44_w_result_range1651w(i);
END GENERATE loop15;
wire_add_sub42_w_lg_cout1654w(0) <= NOT wire_add_sub42_cout;
loop16 : FOR i IN 0 TO 12 GENERATE
wire_add_sub42_w_lg_w_lg_w_lg_cout1654w1655w1656w(i) <= wire_add_sub42_w_lg_w_lg_cout1654w1655w(i) OR wire_add_sub42_w_lg_cout1652w(i);
END GENERATE loop16;
add_sub42 : lpm_add_sub
GENERIC MAP (
LPM_WIDTH => 14,
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO"
)
PORT MAP (
add_sub => rom_mux_w(2),
cout => wire_add_sub42_cout,
dataa => Rk_adder_padded_w(13 DOWNTO 0),
datab => qkd_mux_w(13 DOWNTO 0),
result => wire_add_sub42_result
);
wire_add_sub43_w_result_range1653w <= wire_add_sub43_result(12 DOWNTO 0);
add_sub43 : lpm_add_sub
GENERIC MAP (
LPM_WIDTH => 13,
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO"
)
PORT MAP (
add_sub => rom_mux_w(2),
cin => wire_gnd,
dataa => Rk_adder_padded_w(26 DOWNTO 14),
datab => qkd_mux_w(26 DOWNTO 14),
result => wire_add_sub43_result
);
wire_add_sub44_w_result_range1651w <= wire_add_sub44_result(12 DOWNTO 0);
add_sub44 : lpm_add_sub
GENERIC MAP (
LPM_WIDTH => 13,
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO"
)
PORT MAP (
add_sub => rom_mux_w(2),
cin => wire_vcc,
dataa => Rk_adder_padded_w(26 DOWNTO 14),
datab => qkd_mux_w(26 DOWNTO 14),
result => wire_add_sub44_result
);
loop17 : FOR i IN 0 TO 3 GENERATE
loop18 : FOR j IN 0 TO 26 GENERATE
wire_mux41_data_2d(i, j) <= qkd_mux_input_w(i*27+j);
END GENERATE loop18;
END GENERATE loop17;
mux41 : lpm_mux
GENERIC MAP (
LPM_SIZE => 4,
LPM_WIDTH => 27,
LPM_WIDTHS => 2
)
PORT MAP (
data => wire_mux41_data_2d,
result => wire_mux41_result,
sel => rom_mux_w(1 DOWNTO 0)
);
qds_block40 : altfp_div0_qds_block_6a7
PORT MAP (
aclr => aclr,
clken => clken,
clock => clock,
decoder_bus => rom_add_w,
decoder_output => wire_qds_block40_decoder_output
);
END RTL; --altfp_div0_srt_block_int_91k
--srt_block_int CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix" OPTIMIZE="AREA" POSITION="FIRST" WIDTH_DIV=24 WIDTH_RK_IN=24 WIDTH_RK_OUT=25 WIDTH_ROM=3 WIDTH_ROM_ADD=12 aclr clken clock divider divider_reg Rk Rk_next rom
--VERSION_BEGIN 7.2 cbx_altbarrel_shift 2007:06:21:18:04:30:SJ cbx_altfp_div 2007:07:16:18:07:06:SJ cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_divide 2007:01:30:03:58:02:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ VERSION_END
--qds_block CBX_AUTO_BLACKBOX="ALL" FIRST_QDS="YES" aclr clken clock decoder_bus decoder_output
--VERSION_BEGIN 7.2 cbx_altbarrel_shift 2007:06:21:18:04:30:SJ cbx_altfp_div 2007:07:16:18:07:06:SJ cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_divide 2007:01:30:03:58:02:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ VERSION_END
LIBRARY lpm;
USE lpm.lpm_components.all;
--synthesis_resources = lpm_compare 4 lpm_mux 1 lut 2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altfp_div0_qds_block_7o8 IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
decoder_bus : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
decoder_output : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END altfp_div0_qds_block_7o8;
ARCHITECTURE RTL OF altfp_div0_qds_block_7o8 IS
ATTRIBUTE synthesis_clearbox : boolean;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL q_next_dffe : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_cmpr51_aleb : STD_LOGIC;
SIGNAL wire_cmpr52_aleb : STD_LOGIC;
SIGNAL wire_cmpr53_aleb : STD_LOGIC;
SIGNAL wire_cmpr54_aleb : STD_LOGIC;
SIGNAL wire_mux50_data_2d : STD_LOGIC_2D(15 DOWNTO 0, 31 DOWNTO 0);
SIGNAL wire_mux50_result : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_qds_block45_w_lg_w_k_comp_w_range1770w1780w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_qds_block45_w_lg_w_k_comp_w_range1772w1782w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_qds_block45_w_lg_w_k_comp_w_range1768w1779w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_qds_block45_w_lg_w_k_comp_w_range1771w1781w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_qds_block45_w_lg_w_k_comp_w_range1772w1776w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_qds_block45_w_lg_w_lg_w_k_comp_w_range1772w1782w1783w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_qds_block45_w_lg_w_lg_w_k_comp_w_range1772w1776w1777w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL decoder_output_w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL Div_w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL k_comp_w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL mk_bus_const_w : STD_LOGIC_VECTOR (511 DOWNTO 0);
SIGNAL mk_bus_w : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL mk_neg1_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL mk_pos0_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL mk_pos1_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL mk_pos2_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL q_next_w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL Rk_in_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL Rk_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_qds_block45_w_k_comp_w_range1768w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_qds_block45_w_k_comp_w_range1770w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_qds_block45_w_k_comp_w_range1771w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_qds_block45_w_k_comp_w_range1772w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_qds_block45_w_q_next_w_range1785w : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
wire_qds_block45_w_lg_w_k_comp_w_range1770w1780w(0) <= wire_qds_block45_w_k_comp_w_range1770w(0) AND wire_qds_block45_w_lg_w_k_comp_w_range1768w1779w(0);
wire_qds_block45_w_lg_w_k_comp_w_range1772w1782w(0) <= wire_qds_block45_w_k_comp_w_range1772w(0) AND wire_qds_block45_w_lg_w_k_comp_w_range1771w1781w(0);
wire_qds_block45_w_lg_w_k_comp_w_range1768w1779w(0) <= NOT wire_qds_block45_w_k_comp_w_range1768w(0);
wire_qds_block45_w_lg_w_k_comp_w_range1771w1781w(0) <= NOT wire_qds_block45_w_k_comp_w_range1771w(0);
wire_qds_block45_w_lg_w_k_comp_w_range1772w1776w(0) <= NOT wire_qds_block45_w_k_comp_w_range1772w(0);
wire_qds_block45_w_lg_w_lg_w_k_comp_w_range1772w1782w1783w(0) <= wire_qds_block45_w_lg_w_k_comp_w_range1772w1782w(0) OR wire_qds_block45_w_lg_w_k_comp_w_range1770w1780w(0);
wire_qds_block45_w_lg_w_lg_w_k_comp_w_range1772w1776w1777w(0) <= wire_qds_block45_w_lg_w_k_comp_w_range1772w1776w(0) OR wire_qds_block45_w_k_comp_w_range1768w(0);
decoder_output <= decoder_output_w;
decoder_output_w <= ( "0" & q_next_dffe);
Div_w <= decoder_bus(3 DOWNTO 0);
k_comp_w <= ( wire_cmpr54_aleb & wire_cmpr53_aleb & wire_cmpr52_aleb & wire_cmpr51_aleb);
mk_bus_const_w <= ( "01011101000111111110000110100011" & "01011010000111101110001010100110" & "01010111000111011110001110101001" & "01010100000111001110010010101100" & "01010001000110111110010110101111" & "01001110000110101110011010110010" & "01001011000110011110011110110101" & "01001000000110001110100010111000" & "01000101000101111110100110111011" & "01000010000101101110101010111110" & "00111111000101011110101111000001" & "00111100000101001110110011000100" & "00111001000100111110110111000111" & "00110110000100101110111011001010" & "00110011000100011110111111001101" & "00110000000100001111000011010000");
mk_bus_w <= wire_mux50_result;
mk_neg1_w <= ( mk_bus_w(7) & mk_bus_w(7 DOWNTO 0));
mk_pos0_w <= ( mk_bus_w(15) & mk_bus_w(15 DOWNTO 8));
mk_pos1_w <= ( mk_bus_w(23) & mk_bus_w(23 DOWNTO 16));
mk_pos2_w <= ( mk_bus_w(31) & mk_bus_w(31 DOWNTO 24));
q_next_w <= ( k_comp_w(1) & wire_qds_block45_w_lg_w_lg_w_k_comp_w_range1772w1776w1777w & wire_qds_block45_w_lg_w_lg_w_k_comp_w_range1772w1782w1783w);
Rk_in_w <= ( decoder_bus(11 DOWNTO 4) & "0");
Rk_w <= Rk_in_w;
wire_qds_block45_w_k_comp_w_range1768w(0) <= k_comp_w(0);
wire_qds_block45_w_k_comp_w_range1770w(0) <= k_comp_w(1);
wire_qds_block45_w_k_comp_w_range1771w(0) <= k_comp_w(2);
wire_qds_block45_w_k_comp_w_range1772w(0) <= k_comp_w(3);
wire_qds_block45_w_q_next_w_range1785w <= q_next_w(1 DOWNTO 0);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN q_next_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN q_next_dffe <= q_next_w(1 DOWNTO 0);
END IF;
END IF;
END PROCESS;
cmpr51 : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
aleb => wire_cmpr51_aleb,
dataa => Rk_w,
datab => mk_neg1_w
);
cmpr52 : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "SIGNED",
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