encode3.vhd

来自「使用VHDL语言进行的数字锁相环的设计」· VHDL 代码 · 共 55 行

  -------------------------------------------------------------
  --Copyright (C), 2004- , Huangwei.                         --
  --File name:decode3(归零码生成器)                          --
  --Author:huangwei       Version:1.0        Date:2004/11/24 --
  --Description:                                             --
  --该程序主要完成的功能是将已经编好的HDB3码由NRZ码          --
  --转换成归零码                                             --
  -------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity encode3 is

port(
     clk:in std_logic;           --输入时钟，2M
     datain: in std_logic;       --NRZ码数据输入
     
     dataout: out std_logic      --归零码数据输出
     );
     
end encode3;

architecture encode3_arc of encode3 is

signal count: std_logic;        --计数器寄存器

begin

process(clk,count,datain)

begin

if rising_edge(clk) then

    count <= not count;

end if;

case count is

    when '0' => dataout <= datain;
    when '1' => dataout <= '0';
    when others => null;
    
end case;

end process;

end encode3_arc;