decode1.vhd
来自「使用VHDL语言进行的数字锁相环的设计」· VHDL 代码 · 共 74 行
VHD
74 行
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--Copyright (C), 2004- , Huangwei. --
--File name:decode1(解码器) --
--Author:huangwei Version:1.0 Date:2004/11/24 --
--Description: --
--该程序主要完成的功能是识别数据流中的4连零破坏点; --
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity decode1 is
port(
HDB3_in1:in std_logic; --正1HDB3码数据流
HDB3_in2:in std_logic; --负1HDB3码数据流
clk:in std_logic; --本地时钟
reset:in std_logic; --复位
dataout:out std_logic; --数据输出
point_v:out std_logic --破坏点记录信号
);
end decode1;
architecture decode1_arc of decode1 is
signal buff_1:std_logic_vector(3 downto 0); --正1HDB3码数据流寄存器
signal buff_2:std_logic_vector(3 downto 0); --负1HDB3码数据流寄存器
signal sf_v:std_logic_vector(1 downto 0); --正负极性寄存器
begin
process(clk,reset)
begin
if (reset = '1') then
buff_1 <= "1111";
buff_2 <= "1111";
elsif (clk'event and clk = '0') then
buff_1 <= buff_1(2 downto 0) & HDB3_in1; --数据寄存
buff_2 <= buff_2(2 downto 0) & HDB3_in2;
dataout <= (buff_1(3) or buff_2(3));
if (HDB3_in1 = '1') then --正负极性寄存
sf_v <= sf_v(0) & '1';
elsif (HDB3_in2 = '1') then
sf_v <= sf_v(0) & '0';
end if;
if (((buff_1 = "0001" and buff_2 = "0000") --破坏点判决
or (buff_1= "0000" and buff_2 = "1001")
or (buff_2 = "0001" and buff_1= "0000")
or (buff_2 = "0000" and buff_1= "1001"))
and ((sf_v (0) xor sf_v(1)) = '0')) then
point_v <= '0';
else
point_v <= '1';
end if;
end if;
end process;
end decode1_arc;
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