fenpin.vhd

使用VHDL语言进行的数字锁相环的设计

  -------------------------------------------------------------
  --Copyright (C), 2004- , Huangwei.                         --
  --File name:fenpin(分频器)                                 --
  --Author:huangwei       Version:1.0        Date:2004/11/24 --
  --Description:                                             --
  --该程序主要完成的功能是用于同步锁相环中的分频功能;        --
  -------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fenpin is

port(
     clkin:in std_logic;
     
     clkout1:out std_logic;
     clkout2:out std_logic
     );

end fenpin;

architecture fenpin_arc of fenpin is

signal count1:integer range 0 to 7;    --计数寄存器1
signal clkbuff1:std_logic;

signal count2:integer range 0 to 3;    --计数寄存器2
signal clkbuff2:std_logic;

begin
    
    process(clkin,count1,count2)
        
    begin
        if rising_edge(clkin) then    --计数、分频1
            
            if (count1 >= 7) then
                count1 <= 0; 
                clkbuff1 <= not clkbuff1;
            else
                count1 <= count1 + 1;
                clkout1 <= clkbuff1;
            end if; 

        end if;
        
        if rising_edge(clkin) then    --计数、分频2
            
            if (count2 >= 3) then
                count2 <= 0; 
                clkbuff2 <= not clkbuff2;
            else
                count2 <= count2 + 1;
                clkout2 <= clkbuff2;
            end if; 

        end if;

    
    end process;
    
end fenpin_arc;