jiajian.vhd

使用VHDL语言进行的数字锁相环的设计

  ---------------------------------------------------------------
  --Copyright (C), 2004- , Huangwei.                           --
  --File name:jiajian(相位修正器)                              --
  --Author:huangwei       Version:1.0        Date:2004/11/24   --
  --Description:                                               --
  --该程序主要完成的功能是用于同步锁相环中的加减脉冲功能       --
  --从而实现相位的修正;                                        --
  --其输入端是来自计数器的输出信号(指示是否加或减一个相位修正) --
  --输出端是修正过的同步脉冲.                                  --
  ---------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity jiajian is

port(
     --en : in std_logic;
     insert:in std_logic;
     deduct:in std_logic;
     clkin:in std_logic;           --时钟
     reset:in std_logic;       --复位
     
     clkout:out std_logic      --输出时钟
     );

end jiajian;

architecture jiajian_arc of jiajian is

signal count:integer range 0 to 7;     ----计数寄存器

begin

process(reset,clkin,count,insert,deduct)
    
begin

if (reset = '1') then

    count <= 0;
        
elsif rising_edge(clkin) then
     
            
            if ( (deduct = '1' ) and (insert = '0') ) then         --出现滞后脉冲，扣除一个主时钟脉冲

                if (count = 7) then      
                   count <= 1;
                elsif (count = 6) then
                   count <= 0;
                else
                    count <= count + 2;
                end if;

            elsif ( (deduct = '0' ) and (insert = '1') ) then     --出现超前脉冲，增加一个主时钟脉冲
                
                count <= count;
            
            elsif ( (deduct = '0' ) and (insert = '0') ) then     --实现同步时，正常分频
               
                if (count = 7) then      
                   count <= 0;
                else
                    count <= count + 1;
                end if;
            
            end if;
end if;
    
case count is          --不同的计数值时的数据输出情况
       
    when 4|5|6|7 => clkout <= '1';
    when 0|1|2|3 => clkout <='0';            
    when others => null;
            
end case;
        
end process;

end jiajian_arc;