fenpin2.vhd

使用VHDL语言进行的数字锁相环的设计

  -------------------------------------------------------------
  --Copyright (C), 2004- , Huangwei.                         --
  --File name:fenpin(分频器)                                 --
  --Author:huangwei       Version:1.0        Date:2004/11/24 --
  --Description:                                             --
  --该程序主要完成的功能是用于同步锁相环中的分频功能;        --
  -------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fenpin2 is

port(
     clkin:in std_logic;
     
     clkout:out std_logic
     );

end fenpin2;

architecture fenpin2_arc of fenpin2 is

signal count:std_logic;    --计数寄存器1

begin
    
process(clkin,count)
        
begin

if (clkin'event and clkin = '1') then    --计数、分频

    count <=not count;
    clkout <= count;

end if;

end process;
    
end fenpin2_arc;