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📄 altsyncram_5071.tdf

📁 驱动时钟加入了PLL,使得DDS的驱动时钟可变.32位的NCO使得DDS的分辨率可以做到Hz量级
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123 
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 8,
			PORT_A_LAST_ADDRESS = 12287,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 12,
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a33 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 9,
			PORT_A_LAST_ADDRESS = 12287,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 12,
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a34 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 10,
			PORT_A_LAST_ADDRESS = 12287,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 12,
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a35 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 11,
			PORT_A_LAST_ADDRESS = 12287,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 12,
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a36 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 12,
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a37 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 12,
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a38 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 12,
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a39 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 12,
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a40 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 12,
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a41 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 12,
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a42 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 12,
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a43 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 12,
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a44 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 8,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 12,
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a45 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 9,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 12,
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a46 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 10,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 12,
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a47 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 11,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 12,
			RAM_BLOCK_TYPE = "AUTO"
		);
	address_a_sel[1..0]	: WIRE;
	address_a_wire[13..0]	: WIRE;

BEGIN 
	address_reg_a[].clk = clock0;
	address_reg_a[].d = address_a_sel[];
	out_address_reg_a[].clk = clock0;
	out_address_reg_a[].d = address_reg_a[].q;
	deep_decode.data[1..0] = address_a_wire[13..12];
	deep_decode.enable = B"1";
	mux2.data[] = ( ram_block1a[47..0].portadataout[0..0]);
	mux2.sel[] = out_address_reg_a[].q;
	ram_block1a[47..0].clk0 = clock0;
	ram_block1a[47..0].ena0 = ( deep_decode.eq[3..3], deep_decode.eq[3..3], deep_decode.eq[3..3], deep_decode.eq[3..3], deep_decode.eq[3..3], deep_decode.eq[3..3], deep_decode.eq[3..3], deep_decode.eq[3..3], deep_decode.eq[3..3], deep_decode.eq[3..3], deep_decode.eq[3..3], deep_decode.eq[3..2], deep_decode.eq[2..2], deep_decode.eq[2..2], deep_decode.eq[2..2], deep_decode.eq[2..2], deep_decode.eq[2..2], deep_decode.eq[2..2], deep_decode.eq[2..2], deep_decode.eq[2..2], deep_decode.eq[2..2], deep_decode.eq[2..2], deep_decode.eq[2..1], deep_decode.eq[1..1], deep_decode.eq[1..1], deep_decode.eq[1..1], deep_decode.eq[1..1], deep_decode.eq[1..1], deep_decode.eq[1..1], deep_decode.eq[1..1], deep_decode.eq[1..1], deep_decode.eq[1..1], deep_decode.eq[1..1], deep_decode.eq[1..0], deep_decode.eq[0..0], deep_decode.eq[0..0], deep_decode.eq[0..0], deep_decode.eq[0..0], deep_decode.eq[0..0], deep_decode.eq[0..0], deep_decode.eq[0..0], deep_decode.eq[0..0], deep_decode.eq[0..0], deep_decode.eq[0..0], deep_decode.eq[0..0]);
	ram_block1a[47..0].portaaddr[] = ( address_a_wire[11..0]);
	address_a_sel[1..0] = address_a[13..12];
	address_a_wire[] = address_a[];
	q_a[] = mux2.result[];
END;
--VALID FILE
123

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