registerf.v

来自「驱动时钟加入了PLL,使得DDS的驱动时钟可变.32位的NCO使得DDS的分辨率」· Verilog 代码 · 共 20 行

module registerf(data_f,clk,reset,freq,iwr);
input clk,reset,iwr;
input [31:0]data_f;
output [31:0]freq;
reg [31:0]freq;

always@(posedge clk or posedge reset)
begin 
     if(reset) 
       freq<=0;
     else
       begin
          if(iwr)
            freq<=data_f;
       end
end
endmodule