复件 dds_new.v

来自「驱动时钟加入了PLL,使得DDS的驱动时钟可变.32位的NCO使得DDS的分辨率」· Verilog 代码 · 共 53 行

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

module dds_new(
	aclr,
	clk50,
	freq,
	phase,
	A,
	sinout
);

input	aclr;
input	clk50;
input	[31:0] freq;
input	[31:0] phase;
output	[31:0] A;
output	[11:0] sinout;

wire	[31:18] A_ALTERA_SYNTHESIZED;
wire	SYNTHESIZED_WIRE_4;
wire	[31:0] SYNTHESIZED_WIRE_5;





acc	b2v_inst(.clock(SYNTHESIZED_WIRE_4),
.aclr(aclr),.dataa(freq),.datab(SYNTHESIZED_WIRE_5),.result(SYNTHESIZED_WIRE_5));

add	b2v_inst1(.dataa(phase),
.datab(SYNTHESIZED_WIRE_5),.result(A));

pll	b2v_inst2(.inclk0(clk50),
.c0(SYNTHESIZED_WIRE_4));

sinrom	b2v_inst3(.clock(SYNTHESIZED_WIRE_4),
.address(A_ALTERA_SYNTHESIZED),.q(sinout));


endmodule