adder4_tb.v

来自「是用verilog写得加法器以及计数器里面有测试文件（testbench）」· Verilog 代码 · 共 33 行

`timescale	1ns/1ns

module	adder_tb;
reg	[3:0]	a,b;
reg			cin;
wire[3:0]	sum;
wire		cout;
integer		i,j;

adder4	adder(.sum(sum),.cout(cout),.a(a),.b(b),.cin(cin));
always	#5	cin=~cin;

initial
	begin
		a=0;
		b=0;
		cin=0;
	for(i=1;i<16;i=i+1)
		#10	a=i;
	end
	
initial
	begin
	for(j=1;j<16;j=j+1)
	#10	b=j;
	end
	
initial
	begin
		$monitor($time,,,"%d+%d+%b={%b,%d}",a,b,cin,cout,sum);
		#160	$finish;
	end
endmodule