counter4.v

来自「是用verilog写得加法器以及计数器里面有测试文件（testbench）」· Verilog 代码 · 共 14 行

module	counter4(clk,reset,q);
input	clk,reset;
output	q;
reg[3:0]q;

always	@(posedge	clk)
	begin
		if(!reset)
			q<=1'b0;
		else
			q<=q+1;
	end
endmodule