counter4_tb.v

来自「是用verilog写得加法器以及计数器里面有测试文件（testbench）」· Verilog 代码 · 共 21 行

`timescale	1ns/1ns
module		counter4_tb;
reg			clk,reset;
wire[3:0]	q;
parameter	DELY=100;

counter4	mycounter4(.q(q),.reset(reset),.clk(clk));

always	#(DELY/2)	clk=~clk;
initial
	begin
			clk=0;
			reset=0;
	#DELY	reset=1;
	#DELY	reset=0;
	#(DELY*20)	$finish;
	end
	
initial
$monitor($time,,,"clk=%d	reset=%d	q=%d",clk,reset,q);
endmodule