lcdcont.tan.qmsg

用vhdl语言实现2DPSK数字传输

{ "Info" "ITDB_TSU_RESULT" "cir_shifter:mycir_shift\|ql\[2\] lock clk 0.295 ns register " "Info: tsu for register \"cir_shifter:mycir_shift\|ql\[2\]\" (data pin = \"lock\", clock pin = \"clk\") is 0.295 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.470 ns + Longest pin register " "Info: + Longest pin to register delay is 8.470 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns lock 1 PIN PIN_43 31 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_43; Fanout = 31; PIN Node = 'lock'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "" { lock } "NODE_NAME" } "" } } { "lcdcont.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.747 ns) + CELL(0.591 ns) 8.470 ns cir_shifter:mycir_shift\|ql\[2\] 2 REG LC_X10_Y8_N8 1 " "Info: 2: + IC(6.747 ns) + CELL(0.591 ns) = 8.470 ns; Loc. = LC_X10_Y8_N8; Fanout = 1; REG Node = 'cir_shifter:mycir_shift\|ql\[2\]'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "7.338 ns" { lock cir_shifter:mycir_shift|ql[2] } "NODE_NAME" } "" } } { "cir_shifter.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/cir_shifter.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.723 ns 20.34 % " "Info: Total cell delay = 1.723 ns ( 20.34 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.747 ns 79.66 % " "Info: Total interconnect delay = 6.747 ns ( 79.66 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "8.470 ns" { lock cir_shifter:mycir_shift|ql[2] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "8.470 ns" { lock lock~combout cir_shifter:mycir_shift|ql[2] } { 0.000ns 0.000ns 6.747ns } { 0.000ns 1.132ns 0.591ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "cir_shifter.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/cir_shifter.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.508 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 8.508 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 16; CLK Node = 'clk'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "" { clk } "NODE_NAME" } "" } } { "lcdcont.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clockdiv:div\|clockout 2 REG LC_X11_Y7_N8 92 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X11_Y7_N8; Fanout = 92; REG Node = 'clockdiv:div\|clockout'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "3.032 ns" { clk clockdiv:div|clockout } "NODE_NAME" } "" } } { "clockdiv.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/clockdiv.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.395 ns) + CELL(0.918 ns) 8.508 ns cir_shifter:mycir_shift\|ql\[2\] 3 REG LC_X10_Y8_N8 1 " "Info: 3: + IC(3.395 ns) + CELL(0.918 ns) = 8.508 ns; Loc. = LC_X10_Y8_N8; Fanout = 1; REG Node = 'cir_shifter:mycir_shift\|ql\[2\]'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "4.313 ns" { clockdiv:div|clockout cir_shifter:mycir_shift|ql[2] } "NODE_NAME" } "" } } { "cir_shifter.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/cir_shifter.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns 39.67 % " "Info: Total cell delay = 3.375 ns ( 39.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.133 ns 60.33 % " "Info: Total interconnect delay = 5.133 ns ( 60.33 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "8.508 ns" { clk clockdiv:div|clockout cir_shifter:mycir_shift|ql[2] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "8.508 ns" { clk clk~combout clockdiv:div|clockout cir_shifter:mycir_shift|ql[2] } { 0.000ns 0.000ns 1.738ns 3.395ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "8.470 ns" { lock cir_shifter:mycir_shift|ql[2] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "8.470 ns" { lock lock~combout cir_shifter:mycir_shift|ql[2] } { 0.000ns 0.000ns 6.747ns } { 0.000ns 1.132ns 0.591ns } } } { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "8.508 ns" { clk clockdiv:div|clockout cir_shifter:mycir_shift|ql[2] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "8.508 ns" { clk clk~combout clockdiv:div|clockout cir_shifter:mycir_shift|ql[2] } { 0.000ns 0.000ns 1.738ns 3.395ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk data_out\[6\] lcd:mylcd\|lcd_data\[6\] 12.008 ns register " "Info: tco from clock \"clk\" to destination pin \"data_out\[6\]\" through register \"lcd:mylcd\|lcd_data\[6\]\" is 12.008 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.508 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.508 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 16; CLK Node = 'clk'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "" { clk } "NODE_NAME" } "" } } { "lcdcont.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clockdiv:div\|clockout 2 REG LC_X11_Y7_N8 92 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X11_Y7_N8; Fanout = 92; REG Node = 'clockdiv:div\|clockout'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "3.032 ns" { clk clockdiv:div|clockout } "NODE_NAME" } "" } } { "clockdiv.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/clockdiv.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.395 ns) + CELL(0.918 ns) 8.508 ns lcd:mylcd\|lcd_data\[6\] 3 REG LC_X16_Y10_N2 1 " "Info: 3: + IC(3.395 ns) + CELL(0.918 ns) = 8.508 ns; Loc. = LC_X16_Y10_N2; Fanout = 1; REG Node = 'lcd:mylcd\|lcd_data\[6\]'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "4.313 ns" { clockdiv:div|clockout lcd:mylcd|lcd_data[6] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns 39.67 % " "Info: Total cell delay = 3.375 ns ( 39.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.133 ns 60.33 % " "Info: Total interconnect delay = 5.133 ns ( 60.33 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "8.508 ns" { clk clockdiv:div|clockout lcd:mylcd|lcd_data[6] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "8.508 ns" { clk clk~combout clockdiv:div|clockout lcd:mylcd|lcd_data[6] } { 0.000ns 0.000ns 1.738ns 3.395ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.124 ns + Longest register pin " "Info: + Longest register to pin delay is 3.124 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:mylcd\|lcd_data\[6\] 1 REG LC_X16_Y10_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y10_N2; Fanout = 1; REG Node = 'lcd:mylcd\|lcd_data\[6\]'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "" { lcd:mylcd|lcd_data[6] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.802 ns) + CELL(2.322 ns) 3.124 ns data_out\[6\] 2 PIN PIN_109 0 " "Info: 2: + IC(0.802 ns) + CELL(2.322 ns) = 3.124 ns; Loc. = PIN_109; Fanout = 0; PIN Node = 'data_out\[6\]'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "3.124 ns" { lcd:mylcd|lcd_data[6] data_out[6] } "NODE_NAME" } "" } } { "lcdcont.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns 74.33 % " "Info: Total cell delay = 2.322 ns ( 74.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.802 ns 25.67 % " "Info: Total interconnect delay = 0.802 ns ( 25.67 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "3.124 ns" { lcd:mylcd|lcd_data[6] data_out[6] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "3.124 ns" { lcd:mylcd|lcd_data[6] data_out[6] } { 0.000ns 0.802ns } { 0.000ns 2.322ns } } }  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "8.508 ns" { clk clockdiv:div|clockout lcd:mylcd|lcd_data[6] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "8.508 ns" { clk clk~combout clockdiv:div|clockout lcd:mylcd|lcd_data[6] } { 0.000ns 0.000ns 1.738ns 3.395ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "3.124 ns" { lcd:mylcd|lcd_data[6] data_out[6] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "3.124 ns" { lcd:mylcd|lcd_data[6] data_out[6] } { 0.000ns 0.802ns } { 0.000ns 2.322ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "shifter:myshift_high\|qout\[15\] reset clk 4.312 ns register " "Info: th for register \"shifter:myshift_high\|qout\[15\]\" (data pin = \"reset\", clock pin = \"clk\") is 4.312 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.508 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.508 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 16; CLK Node = 'clk'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "" { clk } "NODE_NAME" } "" } } { "lcdcont.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clockdiv:div\|clockout 2 REG LC_X11_Y7_N8 92 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X11_Y7_N8; Fanout = 92; REG Node = 'clockdiv:div\|clockout'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "3.032 ns" { clk clockdiv:div|clockout } "NODE_NAME" } "" } } { "clockdiv.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/clockdiv.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.395 ns) + CELL(0.918 ns) 8.508 ns shifter:myshift_high\|qout\[15\] 3 REG LC_X4_Y4_N6 2 " "Info: 3: + IC(3.395 ns) + CELL(0.918 ns) = 8.508 ns; Loc. = LC_X4_Y4_N6; Fanout = 2; REG Node = 'shifter:myshift_high\|qout\[15\]'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "4.313 ns" { clockdiv:div|clockout shifter:myshift_high|qout[15] } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/shifter.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns 39.67 % " "Info: Total cell delay = 3.375 ns ( 39.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.133 ns 60.33 % " "Info: Total interconnect delay = 5.133 ns ( 60.33 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "8.508 ns" { clk clockdiv:div|clockout shifter:myshift_high|qout[15] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "8.508 ns" { clk clk~combout clockdiv:div|clockout shifter:myshift_high|qout[15] } { 0.000ns 0.000ns 1.738ns 3.395ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "shifter.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/shifter.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.417 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.417 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns reset 1 PIN PIN_42 57 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_42; Fanout = 57; PIN Node = 'reset'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "" { reset } "NODE_NAME" } "" } } { "lcdcont.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.224 ns) + CELL(1.061 ns) 4.417 ns shifter:myshift_high\|qout\[15\] 2 REG LC_X4_Y4_N6 2 " "Info: 2: + IC(2.224 ns) + CELL(1.061 ns) = 4.417 ns; Loc. = LC_X4_Y4_N6; Fanout = 2; REG Node = 'shifter:myshift_high\|qout\[15\]'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "3.285 ns" { reset shifter:myshift_high|qout[15] } "NODE_NAME" } "" } } { "shifter.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/shifter.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns 49.65 % " "Info: Total cell delay = 2.193 ns ( 49.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.224 ns 50.35 % " "Info: Total interconnect delay = 2.224 ns ( 50.35 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "4.417 ns" { reset shifter:myshift_high|qout[15] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "4.417 ns" { reset reset~combout shifter:myshift_high|qout[15] } { 0.000ns 0.000ns 2.224ns } { 0.000ns 1.132ns 1.061ns } } }  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "8.508 ns" { clk clockdiv:div|clockout shifter:myshift_high|qout[15] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "8.508 ns" { clk clk~combout clockdiv:div|clockout shifter:myshift_high|qout[15] } { 0.000ns 0.000ns 1.738ns 3.395ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "4.417 ns" { reset shifter:myshift_high|qout[15] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "4.417 ns" { reset reset~combout shifter:myshift_high|qout[15] } { 0.000ns 0.000ns 2.224ns } { 0.000ns 1.132ns 1.061ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 27 19:56:48 2007 " "Info: Processing ended: Sat Oct 27 19:56:48 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}