lcdcont.map.qmsg

用vhdl语言实现2DPSK数字传输

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Oct 27 19:56:33 2007 " "Info: Processing started: Sat Oct 27 19:56:33 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lcdcont -c lcdcont " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcdcont -c lcdcont" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clockdiv.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clockdiv.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clockdiv-behavioural " "Info: Found design unit 1: clockdiv-behavioural" {  } { { "clockdiv.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/clockdiv.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 clockdiv " "Info: Found entity 1: clockdiv" {  } { { "clockdiv.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/clockdiv.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lcd.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lcd-behavioural " "Info: Found design unit 1: lcd-behavioural" {  } { { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 26 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 lcd " "Info: Found entity 1: lcd" {  } { { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcdcont.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lcdcont.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lcdcont-structural " "Info: Found design unit 1: lcdcont-structural" {  } { { "lcdcont.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 21 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 lcdcont " "Info: Found entity 1: lcdcont" {  } { { "lcdcont.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file top.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Info: Found entity 1: top" {  } { { "top.bdf" "" { Schematic "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/top.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file shifter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 shifter-behave " "Info: Found design unit 1: shifter-behave" {  } { { "shifter.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/shifter.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 shifter " "Info: Found entity 1: shifter" {  } { { "shifter.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/shifter.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cir_shifter.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cir_shifter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cir_shifter-behave " "Info: Found design unit 1: cir_shifter-behave" {  } { { "cir_shifter.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/cir_shifter.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 cir_shifter " "Info: Found entity 1: cir_shifter" {  } { { "cir_shifter.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/cir_shifter.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lcdcont " "Info: Elaborating entity \"lcdcont\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "reset_int lcdcont.vhd(61) " "Info: (10035) Verilog HDL or VHDL information at lcdcont.vhd(61): object \"reset_int\" declared but not used" {  } { { "lcdcont.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 61 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "rw_int lcdcont.vhd(61) " "Info: (10035) Verilog HDL or VHDL information at lcdcont.vhd(61): object \"rw_int\" declared but not used" {  } { { "lcdcont.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 61 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset lcdcont.vhd(72) " "Warning: VHDL Process Statement warning at lcdcont.vhd(72): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "lcdcont.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 72 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd lcd:mylcd " "Info: Elaborating entity \"lcd\" for hierarchy \"lcd:mylcd\"" {  } { { "lcdcont.vhd" "mylcd" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 85 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clockdiv clockdiv:div " "Info: Elaborating entity \"clockdiv\" for hierarchy \"clockdiv:div\"" {  } { { "lcdcont.vhd" "div" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 97 -1 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "clock_int2 clockdiv.vhd(16) " "Info: (10035) Verilog HDL or VHDL information at clockdiv.vhd(16): object \"clock_int2\" declared but not used" {  } { { "clockdiv.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/clockdiv.vhd" 16 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shifter shifter:myshift_high " "Info: Elaborating entity \"shifter\" for hierarchy \"shifter:myshift_high\"" {  } { { "lcdcont.vhd" "myshift_high" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 101 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cir_shifter cir_shifter:mycir_shift " "Info: Elaborating entity \"cir_shifter\" for hierarchy \"cir_shifter:mycir_shift\"" {  } { { "lcdcont.vhd" "mycir_shift" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 115 -1 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "cir_shifter.vhd(46) " "Info: VHDL Case Statement information at cir_shifter.vhd(46): OTHERS choice is never selected" {  } { { "cir_shifter.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/cir_shifter.vhd" 46 0 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "cir_shifter:mycir_shift\|qout\[7\] data_in GND " "Warning: Reduced register \"cir_shifter:mycir_shift\|qout\[7\]\" with stuck data_in port to stuck value GND" {  } { { "cir_shifter.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/cir_shifter.vhd" 9 -1 0 } }  } 0}