📄 lcdcont.fit.rpt
字号:
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 6.25) ; Number of LABs (Total = 24) ;
+--------------------------------------------+------------------------------+
; 1 ; 5 ;
; 2 ; 3 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 3 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 10 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.33) ; Number of LABs (Total = 24) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 3 ;
; 1 Clock ; 22 ;
; 1 Clock enable ; 7 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 6.58) ; Number of LABs (Total = 24) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 5 ;
; 2 ; 3 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 2 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 7 ;
; 11 ; 1 ;
; 12 ; 0 ;
; 13 ; 2 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 3.83) ; Number of LABs (Total = 24) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 7 ;
; 2 ; 7 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 4 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 2 ;
; 9 ; 0 ;
; 10 ; 2 ;
; 11 ; 0 ;
; 12 ; 1 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 7.50) ; Number of LABs (Total = 24) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 4 ;
; 4 ; 1 ;
; 5 ; 7 ;
; 6 ; 4 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 1 ;
; 11 ; 0 ;
; 12 ; 2 ;
; 13 ; 1 ;
; 14 ; 0 ;
; 15 ; 2 ;
; 16 ; 0 ;
; 17 ; 0 ;
; 18 ; 0 ;
; 19 ; 0 ;
; 20 ; 1 ;
+---------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Sat Oct 27 19:56:39 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off lcdcont -c lcdcont
Info: Selected device EPM1270T144C5ES for design "lcdcont"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EPM570T144C5 is compatible
Info: Device EPM570T144I5 is compatible
Info: Device EPM1270T144C5 is compatible
Info: Device EPM1270T144I5 is compatible
Info: No exact pin location assignment(s) for 1 pins of 18 total pins
Info: Pin ser_clk not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 18
Info: Automatically promoted some destinations of signal "clockdiv:div|clockout" to use Global clock
Info: Destination "enable_out" may be non-global or may not use global clock
Info: Destination "clockdiv:div|clockout" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "reset" to use Global clock
Info: Destination "lcd:mylcd|lcd_select" may be non-global or may not use global clock
Info: Destination "lcd:mylcd|lcd_data[4]" may be non-global or may not use global clock
Info: Destination "lcd:mylcd|lcd_data[3]" may be non-global or may not use global clock
Info: Destination "lcd:mylcd|lcd_data[2]" may be non-global or may not use global clock
Info: Destination "lcd:mylcd|lcd_data[1]" may be non-global or may not use global clock
Info: Destination "lcd:mylcd|lcd_data[0]" may be non-global or may not use global clock
Info: Destination "lcd:mylcd|lcd_data[5]" may be non-global or may not use global clock
Info: Destination "lcd:mylcd|lcd_data[6]" may be non-global or may not use global clock
Info: Destination "lcd:mylcd|lcd_data[7]" may be non-global or may not use global clock
Info: Destination "shifter:myshift_low|qout[0]" may be non-global or may not use global clock
Info: Limited to 10 non-global destinations
Info: Pin "reset" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 1 input, 0 output, 0 bidirectional)
Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used -- 23 pins available
Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 11 total pin(s) used -- 19 pins available
Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 1 total pin(s) used -- 29 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used -- 28 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to pin delay of 2.919 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X11_Y10; Fanout = 1; REG Node = 'lcd:mylcd|lcd_data[0]'
Info: 2: + IC(0.597 ns) + CELL(2.322 ns) = 2.919 ns; Loc. = PIN_117; Fanout = 0; PIN Node = 'data_out[0]'
Info: Total cell delay = 2.322 ns ( 79.55 % )
Info: Total interconnect delay = 0.597 ns ( 20.45 % )
Info: Fitter placement operations ending: elapsed time is 00:00:01
Info: Fitter routing operations beginning
Info: Average interconnect usage is 2% of the available device resources. Peak interconnect usage is 3%.
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Sat Oct 27 19:56:43 2007
Info: Elapsed time: 00:00:04
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -